3D Memory Stack Structure With Dummy Vias for Reliable Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving high data storage capacity and integration density while maintaining reliability.
Innovation Solution
The semiconductor device design includes a stack structure with interlayer insulating layers and horizontal layers alternately stacked, featuring gate and insulating horizontal layers, memory and dummy vertical structures, and contact plugs that penetrate these layers, with the memory vertical structure using a different material and extending further into the pattern structure than the dummy vertical structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally instead of two-dimensionally, then data storage capacity increases, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple layers of memory cells vertically. This dimensionality change enables significantly increased data storage capacity within the same footprint area, directly resolving the contradiction between storage capacity and spatial constraints.
Solution Approach 2:
The three-dimensional memory structure is divided into multiple discrete layers with interlayer insulating layers separating them. Each layer can be independently formed and controlled, which manages the complexity by breaking down the three-dimensional structure into manageable two-dimensional segments that are stacked vertically.
2Quantity of substance
If integration density is increased through three-dimensional stacking, then data storage capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
Interlayer insulating layers are formed between memory cell layers during the stacking process, creating predefined separation planes that facilitate precise alignment and positioning. This preliminary structuring enables controlled three-dimensional assembly with high precision requirements to be met through pre-established reference structures.
Solution Approach 2:
Different regions of the stack structure have different properties - interlayer insulating layers provide electrical isolation in specific regions while memory cell layers provide storage functionality in other regions. This local differentiation allows precise control of electrical properties and manufacturing parameters in different zones of the three-dimensional structure.
3Quantity of substance
If three-dimensional stacking is implemented to increase storage capacity, then integration density improves, but reliability challenges increase
Solution Approach 1:
Interlayer insulating layers are extracted and placed between memory cell layers to provide electrical isolation. This separation prevents electrical interference and leakage between adjacent stacked layers, thereby improving the reliability of the three-dimensional memory structure by eliminating a major source of potential failures.
Solution Approach 2:
The interlayer insulating layers act as intermediary structures between adjacent memory cell layers, providing electrical isolation and mechanical support. These intermediary elements facilitate reliable three-dimensional stacking by preventing direct electrical contact between layers that would otherwise cause leakage and reliability issues.
Data Source
AI summary
A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.