3D Memory Stack Layout With Dummy Vias for Contact Alignment
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Solution Overview
Problem
Contemporary semiconductor devices face challenges in achieving high data storage capacity, denser integration density, and reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
The semiconductor device incorporates a stack structure with alternating interlayer insulating layers and horizontal layers, including memory and dummy vertical structures, where the memory vertical structures penetrate gate horizontal layers and extend into a pattern structure, while dummy vertical structures extend further, with contact plugs having uniform upper surfaces, and a staircase region with varying height differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory vertical structures and dummy vertical structures are arranged in a three-dimensional stack structure, then data storage capacity and integration density are improved, but manufacturing precision and structural complexity increase
Solution Approach 1:
The stack structure is divided into multiple distinct regions: memory cell array region with memory vertical structures, staircase region with dummy vertical structures, and isolation regions. This segmentation allows different structural configurations in different areas, simplifying the manufacturing process while maintaining high storage capacity.
Solution Approach 2:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertical stack structures. Memory vertical structures extend in the vertical direction through multiple insulating layers, enabling increased storage capacity without proportionally increasing manufacturing complexity.
2Reliability
If dummy vertical structures extend further downward than memory vertical structures, then structural stability and electrical isolation are improved, but device complexity increases
Solution Approach 1:
Dummy vertical structures serve as intermediary elements between the memory vertical structures and the substrate. These dummy structures provide electrical isolation and structural support, acting as a buffer zone that simplifies the overall device design by handling isolation requirements separately.
Solution Approach 2:
The dummy vertical structures are positioned specifically in the staircase region with different extension depths compared to memory vertical structures. This local differentiation optimizes electrical isolation where needed while maintaining simplicity in the memory cell region.
3Ease of operation
If gate contact plugs and peripheral contact plugs have uniform upper surfaces, then ease of operation and electrical connection efficiency are improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate contact plugs and peripheral contact plugs are designed with uniform upper surfaces at the same elevation level. This equipotential design simplifies subsequent wiring and electrical connection processes, as all contact points are at the same potential plane, making routing easier and more efficient.
4Quantity of substance
If stack structure extends from memory cell array region to staircase region, then data storage capacity is improved, but device complexity and structural arrangement complexity increase
Solution Approach 1:
The stack structure is divided into functionally distinct segments: memory cell array region for data storage, staircase region for electrical isolation and connection, and isolation regions. This segmentation allows each region to be optimized independently while maintaining overall high storage capacity.
Data Source
AI summary
A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.