3D Memory Dynamic Latches for Parallel Sub-Block Programming
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Solution Overview
Problem
Existing memory devices face challenges in programming multiple sub-blocks efficiently due to limited space for latches under the memory array, leading to increased latency and temporal length of program operations, particularly in high-priority and time-sensitive applications.
Innovation Solution
Implementing dynamic latches above a 3D non-volatile memory array, with a fixed number of latches under the array and additional latches positioned above, allowing concurrent programming of multiple sub-blocks using a single programming pulse without increasing the device's footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If latches are positioned under the memory array, then device structure is simplified, but space for latches is limited and programming latency increases
Solution Approach 1:
The patent transitions from placing latches only in the planar layer under the memory array to adding a vertical dimension by positioning additional latches in a separate layer above the memory array. This three-dimensional arrangement allows more latches to be accommodated without increasing the device footprint, thereby reducing programming latency while maintaining structural organization.
2Productivity
If more latches are added to program multiple sub-blocks concurrently, then programming performance improves, but device footprint increases
Solution Approach 1:
The patent utilizes vertical stacking by placing additional latches in a separate layer above the memory array rather than expanding the planar area. This allows the device to accommodate more latches for concurrent programming of multiple sub-blocks without increasing the device footprint, thus improving programming performance while maintaining compact size.
Solution Approach 2:
The patent implements a hierarchical structure where latches are organized in multiple layers with the memory array at the base and additional latch layers stacked above. This nested arrangement allows efficient use of three-dimensional space, enabling more latches to be integrated without proportionally increasing the device footprint.
3Device complexity
If sequential programming of sub-blocks is used, then latch requirements are reduced, but temporal length of program operations increases
Solution Approach 1:
The patent divides the memory array into multiple sub-blocks, each with dedicated latches in separate layers. This segmentation allows independent concurrent programming of multiple sub-blocks using a single programming pulse, significantly reducing the temporal length of program operations compared to sequential programming, while maintaining manageable latch complexity through structured organization.
Data Source
AI summary
Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.