3D Memory Stack Sidewall Edge Pads for TSV-Free Cooling
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Solution Overview
Problem
Existing 2.5D/3D ICs face challenges in power, performance, area, and cost optimization due to bottom/top electrical interconnects, and insufficient heat dissipation from stacked DRAM memory semiconductor dies, leading to elevated chip temperatures.
Innovation Solution
The IC structure incorporates a first memory stack with semiconductor dies having edge pads on sidewalls, connected via RDL structures, and includes thermal conductivity layers between adjacent dies, eliminating the need for through-silicon vias and enhancing heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used for electrical interconnects in stacked semiconductor dies, then electrical connection between dies is achieved, but manufacturing complexity and alignment difficulty increase severely
Solution Approach 1:
The patent extracts the TSV formation process from the semiconductor die manufacturing process. Instead of forming TSVs through the silicon die, the invention uses edge pads located on the sidewalls of the dies, eliminating the need for complex through-silicon via formation and alignment processes while maintaining electrical interconnect functionality between stacked dies
Solution Approach 2:
The patent transitions from planar pad layouts to three-dimensional edge pad configurations on the sidewalls of semiconductor dies. This dimensional change allows electrical interconnects to be formed on the lateral surfaces of the dies, simplifying the manufacturing process by eliminating the need for deep TSV etching and complex alignment procedures
2Productivity
If multiple DRAM memory semiconductor dies are stacked to increase bandwidth, then memory capacity and bandwidth are improved, but heat dissipation capability deteriorates and chip temperature rises
Solution Approach 1:
The patent introduces thermal management functionality in the vertical dimension by placing thermal conductivity layers between stacked semiconductor dies. This three-dimensional thermal conduction path enables efficient heat dissipation from the interior dies to the exterior, allowing high-bandwidth multi-die stacking without excessive temperature rise
Solution Approach 2:
The patent introduces thermal conductivity layers as intermediary structures between adjacent semiconductor dies. These layers act as thermal mediators that facilitate heat transfer from hot dies to cooler exterior dies, enabling effective thermal management in high-density stacked configurations while maintaining high memory bandwidth
3Temperature
If edge pads are located on sidewalls of semiconductor dies, then thermal conductivity is improved and heat dissipation is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the electrical interconnect function into two independent parts: edge pads on sidewalls for thermal management and top/bottom pads for electrical connection. This segmentation allows each feature to be optimized independently, with edge pads positioned for maximum thermal conductivity without compromising electrical alignment precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design optimizes power, performance, and area while reducing costs by improving thermal conductivity and eliminating TSVs, thus addressing heat dissipation issues in high-bandwidth memory stacks.
Implementation Method 1
includes thermal conductivity layers between adjacent dies, eliminating the need for through-silicon vias and enhancing heat dissipation
Data Source
AI summary
An IC structure includes a first memory stack including a plurality of semiconductor die. The plurality of semiconductor memory dies horizontally separate with each other, wherein each semiconductor die includes a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads located on the first sidewall and arranged in multiple rows or two dimensions. The area of the bottom surface or the top surface is larger than that of any sidewall. A first part of the plurality of edge pads is located within a upper portion of the first sidewall of the semiconductor die, a second part of the plurality of edge pads is located within a lower portion of the first sidewall of the semiconductor die.