3D Memory Deformation-Resistant Edge Seal
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Solution Overview
Problem
As the number of word lines increases in three-dimensional memory devices, deformation of memory dies becomes a significant issue, complicating bonding and mounting, and existing technologies lack effective solutions for enhancing the structural integrity of semiconductor dies.
Innovation Solution
A three-dimensional memory device with a deformation-resistant edge structure is developed, featuring a memory die with a first alternating stack of insulating and conductive layers, surrounded by a second alternating stack of spacer dielectric layers, and an edge seal assembly comprising metallic seal structures that extend from the substrate to the bonding surface, providing a protective barrier and enhancing bonding between dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased to achieve higher memory density, then storage capacity is improved, but deformation of memory dies increases
Solution Approach 1:
The patent divides the memory die structure into multiple alternating stacks (first alternating stack of insulating and conductive layers, second alternating stack of dielectric and spacer layers) that are laterally spaced from each other. This segmentation allows the structure to better distribute and manage deformation stresses across multiple independent layers, reducing overall die deformation while maintaining high memory density through the stacked configuration.
Solution Approach 2:
The patent implements a nested structure where the first alternating stack (containing memory elements) is positioned within and surrounded by the second alternating stack (providing mechanical support). The memory-die bonding pads are embedded within dielectric material layers that are themselves part of the larger alternating stack structure. This nested arrangement allows the outer stack to provide structural reinforcement to the inner memory-containing stack, reducing deformation while preserving high-density storage.
2Reliability
If memory die deformation is reduced through structural modifications, then bonding quality is improved, but device complexity increases
Solution Approach 1:
The alternating stacks serve multiple functions simultaneously: the first alternating stack provides memory element support and electrical isolation, the second alternating stack provides mechanical reinforcement and deformation resistance, and both stacks collectively provide lateral spacing for stress distribution. The memory-die bonding pads embedded in dielectric layers serve both as electrical connection points and as structural integration elements. This multi-functionality reduces the need for additional dedicated bonding structures, thereby limiting the increase in device complexity.
3Stability of the object's composition
If alternating stacks with lateral spacing are implemented to reduce deformation, then manufacturing precision requirements increase
Solution Approach 1:
The patent implements different lateral spacing distances between the first and second alternating stacks at different locations within the memory die. This local variation in spacing allows optimization for specific stress patterns and deformation modes in different regions, providing better overall deformation resistance. By allowing local rather than uniform spacing, the manufacturing precision requirements are reduced compared to maintaining identical spacing throughout the entire structure.
Data Source
AI summary
A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.