3D Memory Staircase Edge Seal for Uniform Step Trimming
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Solution Overview
Problem
Three-dimensional memory devices face challenges in reducing staircase region area due to staircase trimming distortion, which affects word line contact via structures and increases the staircase region area, leading to non-uniform step lengths across the semiconductor device wafer.
Innovation Solution
The introduction of a dummy staircase region with a dummy stack containing a substantially planar sidewall reduces staircase trimming distortion by equalizing step widths of stepped surfaces, thereby minimizing the active staircase region area in each memory plane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If staircase regions are formed in three-dimensional memory devices with vertical NAND strings, then the memory device structure enables vertical stacking and higher integration, but non-uniform step lengths in staircase regions cause trimming distortion that increases area and reduces memory cell density
Solution Approach 1:
The patent creates dummy staircase regions that replicate the geometric features of active staircase regions. These dummy regions serve as reference copies during the trimming process, ensuring that the etching and trimming operations produce uniform step widths across both active and dummy regions. This copying approach allows the active staircase regions to achieve precise, uniform dimensions without distortion, thereby increasing memory cell density while maintaining manufacturing precision.
2Manufacturing precision
If dummy staircase regions are added to equalize step widths, then manufacturing precision is improved, but device structure complexity increases
Solution Approach 1:
The dummy staircase regions are created as simplified copies of the active staircase regions, using the same geometric patterns and dimensional parameters. This copying strategy achieves uniform step widths without requiring complex additional structures or processes. The dummy regions are formed using standard photolithography and etching techniques, maintaining process simplicity while improving precision.
3Productivity
If the active staircase region area is reduced to enhance memory cell density, then productivity improves, but manufacturing precision may deteriorate due to smaller feature sizes
Solution Approach 1:
The dummy staircase regions act as reference structures that define the precise dimensional parameters for the active staircase regions. By trimming both active and dummy regions simultaneously using the same photomask and etching conditions, the patent ensures that even small feature sizes are controlled with high precision. The dummy regions serve as process control elements that guarantee uniform step widths are achieved regardless of the reduced active area size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the total area of the staircase region, increasing memory cell density without the need for compensating for distortion, thus improving the uniformity and efficiency of the memory device.
Implementation Method 1
the anisotropic etch step performs an anisotropic etch process that etches unmasked regions of the vertically alternating sequence
Implementation Method 2
the trimming step performs a mask trimming process that isotropically trims each of the memory-region etch masks
Data Source
AI summary
A memory die includes first and second memory-region alternating stacks of memory-region insulating layers and electrically conductive layers that are laterally spaced apart from each other by a respective first portion of a retro-stepped dielectric structure overlying first stepped surfaces of the first and second memory-region alternating stacks, memory opening fill structures located the first and second memory-region alternating stacks, and a peripheral alternating stack of peripheral insulating layers and spacer material which is laterally spaced from the second memory-region alternating stack by a second portion of the retro-stepped dielectric structure overlying second stepped surfaces of the second memory-region alternating stack. Bottom surfaces of the first and second memory-region alternating stacks are spaced apart by a first lateral spacing distance, and bottom surfaces of the second memory alternating stack and the peripheral alternating stack are spaced apart by the first lateral spacing distance.