3D Memory Electrode Stack With Amorphous Silicon Interface
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Solution Overview
Problem
In the manufacturing of semiconductor devices, particularly three-dimensional semiconductor memory, the electrical resistance of electrode material layers becomes high due to the influence of crystallinity from block insulators or barrier metal layers, leading to unfavorable formation of the second layer.
Innovation Solution
The introduction of a thin silicon oxide or amorphous silicon layer between the barrier metal layer and the electrode material layer, using molybdenum or tungsten, which reduces the impact of crystallinity and improves the particle size and roughness of the electrode material layer, thereby lowering electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an electrode material layer is formed directly on a block insulator or barrier metal layer, then the structure is simple, but the electrical resistance becomes high due to crystallinity influence
Solution Approach 1:
An amorphous silicon layer is introduced as an intermediary between the block insulator/barrier metal layer and the electrode material layer. This intermediate layer acts as a mediator that prevents the harmful crystallinity influence from propagating to the electrode material, thereby reducing electrical resistance while maintaining structural feasibility
Solution Approach 2:
The patent employs a composite structure combining amorphous silicon with the electrode material layer. This composite approach leverages the unique properties of amorphous silicon to suppress crystallinity-induced high resistance, achieving improved electrical characteristics through material composition rather than structural complexity
2Reliability
If an amorphous silicon layer is introduced between the barrier metal layer and electrode material layer, then the electrical resistance is reduced, but the device structure becomes more complex
Solution Approach 1:
The amorphous silicon layer is applied locally only at the critical interface between the barrier metal layer and electrode material layer, rather than throughout the entire device structure. This localized application minimizes the increase in overall device complexity while effectively addressing the electrical resistance issue at the specific problem location
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the electrical resistance of the electrode material layer and improves its formation quality, enhancing the performance and reliability of three-dimensional semiconductor memory devices.
Implementation Method 1
it has been found that when a block insulator 5 or a barrier metal layer 6a having a crystalline structure is present, crystallinity is transmitted to an electrode material layer 6c formed on a surface of the block insulator 5 or the barrier metal layer 6a, thereby increasing particle sizes of crystal particles in the electrode material layer 6c and increasing electrical resistance
Implementation Method 2
The introduction of a thin silicon oxide or amorphous silicon layer between the barrier metal layer and the electrode material layer, using molybdenum or tungsten, which reduces the impact of crystallinity and improves the particle size and roughness of the electrode material layer
Data Source
AI summary
In one embodiment, a semiconductor device includes a first layer including a metal element. The device further includes a first insulator that is in contact with the first layer and includes silicon and oxygen. The device further includes a second layer that is in contact with the first insulator and includes molybdenum or tungsten.