3D Semiconductor Memory Device Electrode Pad Positioning

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Solution Overview

Problem

Current three-dimensional semiconductor memory devices face challenges in achieving high integration and efficient signal transfer due to limitations in electrode design and connection structures, which affect performance and cost.

Innovation Solution

The proposed solution involves a three-dimensional semiconductor memory device with a substrate having a cell array region and a connection region, featuring an electrode structure with vertically stacked electrodes and mold patterns, where the pad portions of the electrodes are strategically positioned to overlap the mold patterns, allowing for increased signal transfer speeds and design flexibility through the use of contact plugs that supply operating voltages to opposite ends of the electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If electrodes are vertically stacked to increase integration, then device density is improved, but signal transfer speed deteriorates due to longer signal paths

Engineering Contradiction:
Improvedevice integration densityVSAvoidsignal transfer speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent transitions from planar electrode arrangement to three-dimensional vertically stacked electrodes, utilizing the vertical dimension to increase integration density while managing signal path lengths through strategic pad portion positioning and contact plug connections

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If pad portions are positioned closer to the cell array region, then signal transfer speed is improved, but manufacturing precision deteriorates due to alignment difficulties

Engineering Contradiction:
Improvesignal transfer speedVSAvoidpad portion alignment precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The pad portions of vertically stacked electrodes are nested to overlap each other in the vertical direction, creating a compact structure that maintains short signal paths while providing clear alignment references for manufacturing processes

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

Contact plugs serve as intermediary elements that connect the overlapping pad portions to connection lines, decoupling the alignment requirements between stacked electrodes and the connection network, thereby improving both signal speed and manufacturing precision

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If contact plugs are used to connect electrodes to connection lines, then design flexibility is improved, but device complexity increases

Engineering Contradiction:
Improveconnection design flexibilityVSAvoidstructure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The contact plugs serve multiple functions: electrical connection between electrodes and connection lines, alignment reference for subsequent patterning steps, and structural support for the vertically stacked electrode configuration, thereby reducing overall device complexity despite the added connection elements

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11678488B2Three-dimensional semiconductor memory device
Publication Date: 2023.06.13 SAMSUNG ELECTRONICS CO LTD
  • US11678488B2 patent drawing
  • US11678488B2 patent drawing
  • US11678488B2 patent drawing

AI summary

A three-dimensional semiconductor memory device including: a substrate including a cell array region and a connection region; and an electrode structure extending along a first direction from the cell array region to the connection region and is a plurality of electrodes vertically stacked OD the substrate, each of the electrodes including an electrode portion on the cell array region and a pad portion on the connection region, wherein the electrodes include a first electrode located at a first level from the substrate and a second electrode located at a second level from the substrate, the second level being higher than the first level, and the pad portion of the first electrode is closer to the cell array region than the pad portion of the second electrode.