3D Semiconductor Memory Electrode Stack for Dense Cell Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration density due to the high cost and complexity of forming fine patterns, necessitating the development of three-dimensional semiconductor memory devices with improved reliability and integration density.
Innovation Solution
A 3D semiconductor memory device design featuring a source conductive pattern on a substrate with sequentially stacked electrode structures, including erase control, ground selection, cell gate, and string selection gate electrodes, along with vertically extending semiconductor patterns and data storage patterns, to enhance integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use fine pattern formation techniques to increase integration density, then integration density is improved, but manufacturing cost increases significantly due to the need for extremely high-priced apparatus
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. Multiple memory cell layers are stacked in the vertical direction, allowing integration density to increase without requiring finer lateral patterns. This dimensional change enables continued scaling while avoiding the need for extremely expensive fine pattern formation apparatus.
2Quantity of substance
If two-dimensional semiconductor devices continue to scale to increase integration density, then integration density is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete memory cell layers stacked vertically. Each layer can be formed using similar process steps, allowing modular manufacturing. This segmentation into repeatable units simplifies the overall manufacturing process compared to attempting to create ultra-fine two-dimensional patterns, as the same layer formation processes can be repeated for each vertical stack.
3Quantity of substance
If three-dimensional semiconductor memory devices are designed with vertically stacked electrode structures, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning steps where mandrel structures and spacer structures are formed before the final electrode patterns. These preliminary structures serve as self-aligned templates that define subsequent layer positions, reducing the need for high-precision photolithographic alignment. The spacer structures are conformally deposited on the mandrels, automatically establishing precise vertical and lateral dimensions without requiring additional alignment steps.
Solution Approach 2:
Mandrel structures and spacer structures are introduced as intermediary elements that facilitate the formation of the final electrode patterns. These intermediaries simplify the direct patterning process by providing self-aligned templates, reducing the manufacturing precision requirements for the actual memory electrode formation while still achieving the desired vertical stacking geometry.
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.