3D Memory Cell Electrode Formation in Stable Stacked Structures
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Solution Overview
Problem
The challenge in semiconductor technology is to efficiently manufacture high-density memory cells on a limited substrate while maintaining performance and mechanical stability, as the industry seeks to increase integration and reduce costs.
Innovation Solution
A manufacturing method for a semiconductor device involves sequentially depositing sacrificial layers and insulation layers on a substrate, forming via holes and dummy word lines, and then creating a stacked structure with alternating trenches and grooves. Conductive layers are formed within these grooves, and the conductive layers surrounding the dummy word lines are disconnected to form electrodes for the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more device cells are packed on a limited substrate to reduce cost, then productivity increases, but manufacturing precision and reliability deteriorate due to process variations affecting device performance
Solution Approach 1:
The patent transitions from planar device arrangement to three-dimensional stacked structure, arranging memory cells vertically along the channel length direction. This dimensional change enables higher device density without compromising individual cell performance, as each stacked cell maintains proper electrical isolation and access through source/drain regions positioned at different heights
Solution Approach 2:
The channel region is divided into multiple segments along its length, with source and drain regions creating distinct compartments for individual memory cells. This segmentation allows independent formation and control of each cell's active region, ensuring consistent electrical characteristics even as cell density increases
2Manufacturing precision
If conductive layers replace sacrificial layers in stacked structures, then manufacturing precision improves, but structural stability deteriorates due to potential collapse during the replacement process
Solution Approach 1:
Source and drain regions are formed in advance before the conductive layer replacement process. These pre-formed regions act as structural anchors that maintain the stacked configuration during sacrificial layer removal and subsequent conductive layer deposition, preventing collapse while enabling precise positioning
Solution Approach 2:
The source and drain regions serve as intermediary structural elements that bridge the sacrificial layers and final conductive layers. These regions provide mechanical support during the transition phase, allowing the sacrificial layers to be replaced with precision conductive layers without compromising overall structure integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the creation of densely packed memory cells with improved mechanical stability and efficiency, enabling higher integration densities and reducing the risk of structural collapse during the conductive layer replacement process.
Implementation Method 1
sequentially and alternately depositing a plurality of sacrificial layers and a plurality of insulation layers on the substrate to obtain a stacked structure
Data Source
AI summary
A semiconductor device, manufacturing method therefor, and electronic equipment are provided. The manufacturing method includes: alternately depositing sacrificial layers and insulation layers to obtain a stacked structure; forming in the stacked structure a plurality of via holes distributed at intervals, and forming dummy word lines in the via holes; forming a first trench penetrating through the stacked structure every two via holes apart; forming a plurality of grooves by re-etching the plurality of insulation layers within the first trench, wherein two grooves of each insulation layer in two first trenches respectively expose partial side walls of a dummy word line; forming conductive layers within the two grooves corresponding to each insulation layer, wherein a conductive layer within each groove surrounds two exposed dummy word lines; and disconnecting a conductive layer surrounding a dummy word line to form a first electrode and a second electrode of a transistor.