3D Memory Programming Speed via Electron Drainage
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Solution Overview
Problem
In 3D memory devices, programming from bottom to top can lead to program disturbs and decreased speed due to electron accumulation, which existing methods have not adequately addressed.
Innovation Solution
The introduction of a preparation step after each verification step in the incremental step pulse programming (ISPP) scheme, where the electrons accumulated in the channel are drained by the selected bit line, enhancing coupling and reducing program disturbs while increasing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If programming is performed from bottom to top in 3D memory devices, then programming can be completed systematically through the stack, but electron accumulation in the channel prevents proper pre-charging of the selected word line, causing program disturbs and decreasing program speed
Solution Approach 1:
A preparation step is performed before the actual programming operation to drain accumulated electrons from the channel. This preliminary action removes the harmful electron accumulation that would otherwise prevent proper pre-charging of the selected word line, thereby eliminating program disturbs and enabling faster programming without reliability penalties.
Solution Approach 2:
The preparation step applies a counter-action by draining electrons from the channel before programming begins. This anti-action counteracts the harmful effect of electron accumulation that occurs during bottom-to-top programming, preventing the disturbance mechanism from occurring in the first place and allowing the programming process to proceed at optimal speed.
2Quantity of substance
If electrons are accumulated in the channel during programming, then charge storage occurs, but the selected word line cannot be pre-charged to an appropriate level, causing program disturbs
Solution Approach 1:
The preparation step extracts accumulated electrons from the channel by applying a drain voltage through the selected bit line. This extraction removes the excess charge that would interfere with word line pre-charging, thereby preventing program disturbs while allowing the programming process to maintain necessary charge storage functionality.
Solution Approach 2:
Before the programming operation begins, a preparatory anti-action is applied to remove accumulated electrons from the channel. This preliminary counter-action prevents the harmful interaction between accumulated electrons and the word line pre-charging process, eliminating program disturbs without affecting the overall charge storage capability of the memory device.
3Productivity
If the selected bit line is used to drain electrons during a preparation step, then program disturbs are reduced and program speed increases, but an additional step is required in the programming sequence
Solution Approach 1:
The preparation step is integrated into the programming sequence as a preliminary action that occurs before the main programming operation. By performing electron drainage in advance, the system eliminates program disturbs and enables faster programming, while the additional step is organized in a logical flow that minimizes overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces program disturbs and enhances programming speed by ensuring proper pre-charging and electron drainage, improving the overall efficiency of memory cell programming in 3D memory devices.
Implementation Method 1
a preparation step is performed before a program step, during which electrons accumulated in a channel of a selected NAND string are drained by a selected bit line
Data Source
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AI summary
A vertical NAND string in a channel-stacked 3D memory device may be programmed using ISPP scheme, wherein a preparation step is introduced immediately after each verification step and before the start of a corresponding verification step. During the preparation step, the electrons accumulated in the channel may be drained by the selected bit line for enhancing the coupling effect of the channel, thereby reducing program disturb and increasing program speed.