3D Memory Bit-Line Erase Bias for Truncated Channel Uniformity
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Solution Overview
Problem
Three-dimensional memory devices face challenges in achieving uniform erase speeds for memory strings with truncated and non-truncated channels at the drain select electrodes, as existing technologies struggle to optimize erase operations across different channel types.
Innovation Solution
The implementation of a three-dimensional memory device with alternating stacks of insulating and conductive layers, where first bit lines are biased at a higher erase voltage than second bit lines by a non-zero voltage differential, ensuring uniform erase speeds for both types of memory strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single erase voltage is applied to all bit lines, then the device structure is simple and easy to manufacture, but the erase speeds are non-uniform for memory strings with truncated and non-truncated channels
Solution Approach 1:
The bit lines are segmented into two distinct groups: first bit lines connected to memory strings with truncated channels and second bit lines connected to memory strings with non-truncated channels. Each group is independently biased at different erase voltages during erase operations, allowing optimized erase speeds for each channel type while maintaining separate control circuits for each group
Solution Approach 2:
Different erase voltages are applied to different regions/bit line groups based on their specific channel characteristics. First bit lines receive a first erase voltage optimized for truncated channels, while second bit lines receive a second erase voltage optimized for non-truncated channels, achieving local optimization of erase performance
2Productivity
If different erase voltages are applied to first and second bit lines, then uniform erase speeds are achieved for both truncated and non-truncated channels, but the peripheral circuit complexity increases
Solution Approach 1:
The erase voltage application circuit is designed to dynamically switch between different voltage levels for different bit line groups. The circuit can selectively apply the first erase voltage to first bit lines and the second erase voltage to second bit lines based on which memory strings are being erased, providing adaptive voltage control that optimizes erase efficiency
Solution Approach 2:
The system changes the electrical parameter (erase voltage) based on the type of memory string being erased. By adjusting the voltage parameter differently for first and second bit lines, the system optimizes erase operation efficiency for both truncated and non-truncated channels while managing circuit complexity through parameter variation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient and uniform erase operations across memory strings with truncated and non-truncated channels, enhancing the performance and reliability of three-dimensional memory devices.
Implementation Method 1
a peripheral circuit including an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation, wherein the first bit line erase voltage is greater than the second bit line erase voltage by a non-zero voltage differential
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.