3D Memory Erase-Verify Segmentation and Pass Voltage Masking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Three-dimensional memory systems face challenges in erase-verify operations due to differences in electric field effects across layers, leading to increased residual charges and potential erase-verify failures.

Innovation Solution

Implementing a method where multiple erase-verify operations are performed separately on different groups of memory cells within a memory cell string, using pass voltages to 'mask' residual charges and ensure successful erasure verification by applying distinct voltages to word lines connected to neighboring cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single erase-verify operation is performed on all memory cells in a 3D memory, then the operation is simple and fast, but residual charges cause erase-verify failures due to different electric field effects across layers

Engineering Contradiction:
Improveerase-verify operation reliabilityVSAvoiderase-verify operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory cell string is divided into multiple groups (first group, second group, etc.) based on their vertical positions in the 3D stack. Each group is subjected to separate erase-verify operations, allowing independent control and verification of erasure for cells at different heights, thereby eliminating residual charge interference from upper or lower layers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Before performing the erase-verify operation on a particular group of memory cells, preliminary actions are taken to apply pass voltages to word lines connected to neighboring cells. This preliminary voltage application masks residual charges that could interfere with the current operation, ensuring accurate verification.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If pass voltages are applied to mask residual charges, then erase-verify accuracy is improved, but the operation time and energy consumption increase

Engineering Contradiction:
Improveerase-verify accuracyVSAvoiderase-verify operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

By segmenting the memory cell string into multiple groups and performing erase-verify operations on them sequentially rather than simultaneously, the patent applies pass voltages only when necessary for specific groups, minimizing the total time and energy consumption compared to a single comprehensive operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The erase-verify operation is performed continuously on different groups of memory cells without idle waiting. While one group is being verified, another group can be prepared or verified in parallel, maintaining continuous productive action and reducing overall operation time.

Inventive Principle:
Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the probability of erase-verify failures by effectively managing residual charges and ensuring accurate verification of memory cell erasure across varying layers in 3D memory systems.

Implementation Method 1

the effect of electric field of a erase-verify voltage applied on upper layers of the 3D memory is different from the effect of electric field of the erase-verify voltages applied on lower layers of the 3D memory

Methodology Applied
Scientific EffectElectric Field: Electric Field

Implementation Method 2

In an erase-verify operation, the effect of electric field of a erase-verify voltage applied on upper layers of the 3D memory is different from the effect of electric field of the erase-verify voltages applied on lower layers of the 3D memory

Methodology Applied
Scientific EffectElectrical Conductivity Change: Electrical Resistance

Data Source

PatentUS10340017B2Erase-verify method for three-dimensional memories and memory system
Publication Date: 2019.07.02 MACRONIX INTERNATIONAL CO LTD
  • US10340017B2 patent drawing
  • US10340017B2 patent drawing
  • US10340017B2 patent drawing

AI summary

An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.