3D Memory Vertical Contacts With Etch Stop Wafer Bonding
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Solution Overview
Problem
Planar memory cells face challenges in scaling beyond a certain limit due to increased complexity and cost in fabrication, necessitating a transition to 3D memory architectures to enhance memory density.
Innovation Solution
A method for forming 3D NAND memory devices involves creating an array wafer with alternating dielectric etch stop structures and staircase formations, followed by bonding with a CMOS wafer to establish vertical through contacts, utilizing a flipped array wafer configuration to minimize plasma etching damage to CMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and fabrication processes, then memory density is improved, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture by stacking multiple memory layers vertically. This dimensional change allows continued scaling and density improvement without further reducing lateral feature sizes, thereby avoiding the exponential increase in fabrication complexity and cost associated with sub-10nm planar scaling.
2Reliability
If through substrate contacts are formed in conventional 3D memory devices, then vertical interconnects are established, but plasma etching causes damage to CMOS devices
Solution Approach 1:
The patent forms through substrate contacts to the alternating dielectric etch stop structure BEFORE bonding the array wafer to the CMOS wafer. This preliminary action allows the formation of robust vertical interconnects and etch stop structures that will protect underlying regions during subsequent plasma processing steps, preventing plasma damage to CMOS devices while maintaining interconnect reliability.
Solution Approach 2:
The alternating dielectric etch stop structure serves as an intermediary protective layer between the plasma etching process and the CMOS devices. This multi-layer dielectric structure with varying etch selectivities acts as a buffer that protects underlying CMOS structures from direct plasma exposure and damage during through-contact formation.
3Reliability
If alternating dielectric etch stop structure is formed on the first substrate, then vertical through contacts can be reliably formed, but the structure complexity increases
Solution Approach 1:
The patent segments the dielectric structure into multiple alternating layers with different etch selectivities (e.g., silicon oxide and silicon nitride layers). This segmentation creates distinct etch stop planes that enable reliable vertical contact formation at specific depths while providing controlled access to underlying structures. The segmented approach simplifies the overall fabrication process by enabling selective etching through the stack.
Solution Approach 2:
The alternating dielectric etch stop structure serves multiple functions simultaneously: it provides etch stop planes for vertical contact formation, acts as a protective barrier during plasma processing, enables selective access to different substrate regions, and serves as a template for subsequent staining and imaging processes. This multi-functionality reduces the need for separate protective structures.
Data Source
AI summary
A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an etch stop structure in a first wafer, forming a first through contact in contact with the etch stop structure, bonding the first wafer to a second wafer to electrically connect the first through contact to a CMOS device of the second wafer, and forming a through substrate contact penetrating a first substrate of the first wafer and the etch stop structure, and in electrically contact with the CMOS device through the first through contact.