3D Memory Array Etch Stop Layer for Selective Channel Formation
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Solution Overview
Problem
Current methods for forming three-dimensional vertical NAND strings are complex and time-consuming, involving repeated sidewall spacer formation and etching, which results in conical active regions and limited bit density, and face challenges in achieving precise etching profiles and selectivity in multilayer stacks.
Innovation Solution
A method involving a substrate with a stack of alternating conductive and insulating layers, an etch stop layer, and selective etching processes to form U-shaped semiconductor channels with control gate electrodes, allowing for efficient formation of slit trenches and memory holes without penetrating through sacrificial layers, enabling high-density memory device fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If repeated sidewall spacer formation and etching is used to form active regions, then the active regions can be formed, but the process becomes complex and time-consuming
Solution Approach 1:
The patent introduces an etch stop layer beneath the control gate electrodes before forming the active regions. This preliminary action enables subsequent selective etching processes to precisely define active regions without requiring repeated spacer formation and etching cycles, thereby simplifying the fabrication process while maintaining manufacturing precision
Solution Approach 2:
The patent segments the etching process into distinct stages by using the etch stop layer as a boundary. The first etch chemistry selectively etches through the stack to the etch stop layer, and the second etch chemistry etches through the etch stop layer to the sacrificial feature. This segmentation eliminates the need for repeated spacer formation and etching, reducing process complexity and time
2Manufacturing precision
If conventional etching processes are used without etch stop layer, then etching can proceed, but etching selectivity and precise profile control are difficult to achieve
Solution Approach 1:
The etch stop layer serves as an intermediary between the control gate electrode stack and the sacrificial feature. It provides a selective etching target that enables precise control of the etching profile. The first etch chemistry stops at the etch stop layer, and the second etch chemistry selectively removes the etch stop layer, achieving precise profile control without increasing overall process complexity
Solution Approach 2:
The patent changes the etching parameters by introducing different etch chemistries for different etching stages. The first etch chemistry is selected to etch the stack materials but stop at the etch stop layer, while the second etch chemistry is selected to etch through the etch stop layer. This parameter change enables precise etching profile control
3Manufacturing precision
If etching proceeds through the entire stack without stopping, then complete removal is achieved, but short circuits may occur and bit density is limited
Solution Approach 1:
The etch stop layer is positioned to prevent premature or excessive etching that could cause short circuits. By providing a selective stopping point, it prevents the etch chemistry from removing critical materials that would maintain electrical isolation, thereby preventing short circuits while still achieving complete removal of sacrificial materials where needed
Solution Approach 2:
The patent extracts the etch stop layer function from the bulk stack materials. This dedicated layer is specifically designed to be etched by the second etch chemistry after the first etch chemistry has removed sacrificial materials. This extraction enables complete removal of sacrificial features while maintaining control over when and where etching occurs, preventing short circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, enhances etching selectivity, and allows for the creation of high-density memory devices with improved bit density and reduced complexity, overcoming the limitations of existing methods by using a single-step etch process and minimizing short circuits.
Implementation Method 1
etching the at least one opening in the stack at least to the etch stop layer using a first etch chemistry
Implementation Method 2
further etching the at least one opening through the etch stop layer to the sacrificial feature using a second etch chemistry in which the second etch chemistry is different from the first etch chemistry
Data Source
AI summary
A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.