3D Memory Opening Etch Stop Using Ion-Implanted Sacrificial Fill
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Solution Overview
Problem
Current methods for forming three-dimensional memory devices face challenges in creating precise etch stop layers and maintaining uniformity in memory opening dimensions, leading to variations in device density and performance.
Innovation Solution
The method involves forming a semiconductor structure with alternating stacks of insulating and conductive layers, incorporating a doped inter-tier dielectric layer to enhance etch resistance, and using ion implantation to create a differential etch stop layer, allowing for precise control of memory opening formation and filling with vertical semiconductor channels and memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etch stop layers are used in forming three-dimensional memory devices, then the etching process can proceed, but precise control over memory opening dimensions and uniformity is lost, leading to variations in device density and performance
Solution Approach 1:
The patent applies local quality by creating a dopant concentration gradient within the inter-tier dielectric layer. The dopant concentration varies spatially, with higher concentration near the sacrificial fill material interface and lower concentration toward the alternating stack interface. This gradient provides localized etch resistance exactly where needed during the etching process, enabling precise memory opening dimension control while maintaining process reliability
Solution Approach 2:
The patent utilizes parameter changes by modifying the physical and chemical properties of the inter-tier dielectric layer through controlled dopant incorporation. By adjusting dopant concentration, type, and distribution, the etch resistance, dielectric constant, and mechanical properties of the layer are tuned to achieve optimal etch stop functionality, resulting in improved memory opening uniformity and reduced device performance variations
2Strength
If ion implantation is used to create etch stop layers, then etch resistance is enhanced, but the process complexity and manufacturing steps increase
Solution Approach 1:
The patent merges the formation of the inter-tier dielectric layer with the ion implantation etch stop layer creation process. The dopant ions are implanted directly into the inter-tier dielectric layer during its deposition or shortly thereafter, combining two functions (dielectric formation and etch stop layer creation) into a single integrated process flow, thereby enhancing etch resistance without proportionally increasing overall process complexity
Solution Approach 2:
The patent applies preliminary action by performing ion implantation to create the etch stop layer before the actual memory opening etching process. This pre-prepared dopant-containing layer provides the necessary etch resistance barrier in advance, allowing the subsequent etching to proceed with precise control and reducing the need for complex real-time process adjustments
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved control over memory opening dimensions, increased device density, and reduced variations, resulting in more uniform and efficient three-dimensional memory device fabrication.
Implementation Method 1
doping an upper portion of the sacrificial memory opening fill structure with atoms of at least one dopant species
Data Source
AI summary
A method includes forming a first alternating stack of first insulating layers and first sacrificial material layers over a substrate, forming a first in-process inter-tier dielectric layer over the first alternating stack, forming a first memory opening through the first in-process inter-tier dielectric layer and the first alternating stack, forming a sacrificial memory opening fill structure in the first memory opening, doping an upper portion of the sacrificial memory opening fill structure with atoms of at least one dopant species, forming a second alternating stack of second insulating layers and second sacrificial material layers over the first alternating stack, forming a second memory opening through the second alternating stack by performing an anisotropic etch process, and removing the sacrificial memory opening fill structure.