Stacked-Axis 3D Memory Channels With Etch-Stop Intermediate Layers

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Solution Overview

Problem

In three-dimensional semiconductor memory devices, achieving high shape and dimensional controllability during the etching process for memory holes and slits is challenging due to alignment shifts and etching rate differences between stacked units, leading to potential fluctuations in memory cell characteristics.

Innovation Solution

The introduction of a first intermediate layer with a lower etching rate than electrode and insulating layers, such as a tungsten silicide layer, between stacked units allows for controlled etching of holes and slits, reducing aspect ratio increases and facilitating patterning by acting as an etching stopper and maintaining dimensional consistency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If RIE etching is used to form memory holes and slits in stacked bodies, then high shape controllability and dimensional controllability are desirable, but alignment shifts and etching rate differences between stacked units cause fluctuations in memory cell characteristics

Engineering Contradiction:
Improvedimensional controllabilityVSAvoidmemory cell characteristic consistency
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A first intermediate layer is introduced between stacked units as an intermediary component. This layer has a lower etching rate than the electrode and insulating layers, causing etching to self-stop at this layer. This mediates the etching process to prevent over-etching and alignment shifts, thereby maintaining dimensional controllability and memory cell characteristic consistency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The etching rate parameter is deliberately varied by introducing a material with different etching characteristics (lower etching rate) in the intermediate layer. This parameter change creates a self-stopping etching effect that prevents over-etching and maintains precise dimensional control despite variations between stacked units.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If multiple layers of electrode layers and insulating layers are stacked to form three-dimensional structure, then memory device capacity increases, but aspect ratio increases making etching more difficult

Engineering Contradiction:
Improvememory device capacityVSAvoidetching difficulty
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The first intermediate layer acts as an etching stopper that mediates the etching process through multiple stacked units. By having a lower etching rate, it creates natural stopping points that prevent excessive etching depth, thereby enabling the formation of memory holes and slits even as the number of stacked layers increases and aspect ratio worsens.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The stacked body is segmented into multiple units with intermediate layers between them. This segmentation creates discrete etching zones with controlled depths, allowing the etching process to be effectively managed across multiple layers without the aspect ratio becoming prohibitive.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of memory holes and slits with improved configuration and dimensional controllability, suppressing fluctuations in memory cell characteristics and maintaining the structural integrity of the memory device.

Implementation Method 1

a first intermediate layer made of a different material than the electrode layers and the insulating layers. The first intermediate layer may include a tungsten silicide layer, for example. The first intermediate layer has a lower etching rate than the electrode layers and the insulating layers

Methodology Applied
Scientific EffectEtching rate difference:

Data Source

PatentUS12082413B2Vertical semiconductor memory device having stacked shifted axis channels
Publication Date: 2024.09.03 KIOXIA CORP
  • US12082413B2 patent drawing
  • US12082413B2 patent drawing
  • US12082413B2 patent drawing

AI summary

According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.