3D Memory Device Etch Stop Layer for Plasma Damage Prevention
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Solution Overview
Problem
Conventional 3D memory device fabrication methods face challenges in forming reliable interconnect structures due to high-energy plasma etching, which can damage CMOS devices and affect the reliability of the 3D memory devices.
Innovation Solution
A method for forming a 3D memory device involves creating an array wafer with an etch stop layer and array well structure, bonding it with a CMOS wafer, and using deep plasma etching with an etch stop layer to form through substrate contacts, thereby preventing plasma-induced damage to CMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-energy plasma etching is used to form through substrate contacts, then the etching process can penetrate the substrate effectively, but CMOS devices are damaged by plasma-induced damage
Solution Approach 1:
The substrate is divided into a first substrate (array wafer) and a second substrate (CMOS wafer) that are bonded together. The plasma etching is applied only to the first substrate to form through substrate contacts, while the second substrate containing CMOS devices is protected from plasma exposure. This segmentation allows effective etching penetration without damaging sensitive CMOS devices.
Solution Approach 2:
The CMOS devices are extracted from the array wafer and placed on a separate CMOS wafer before the plasma etching process. This extraction removes the vulnerable CMOS devices from the etching zone, allowing high-energy plasma to be used on the array wafer without causing plasma-induced damage to the CMOS devices.
2Manufacturing precision
If planar memory cells are scaled to smaller sizes by improving process technology, then manufacturing precision is improved, but feature sizes approach a lower limit making planar processes challenging and costly
Solution Approach 1:
The invention transitions from planar memory cell architecture to three-dimensional memory architecture. By stacking multiple layers vertically, the memory density is increased without further reducing the lateral feature sizes of individual memory cells. This dimensional change avoids the limitations and increased complexity associated with scaling planar processes to extremely small dimensions.
3Quantity of substance
If 3D memory architecture is used to address upper density limitation, then memory density is improved, but integration of array wafer and CMOS wafer becomes challenging
Solution Approach 1:
The array wafer and CMOS wafer are prepared separately with pre-formed structures before bonding. Through substrate contacts are formed in the array wafer, and contact holes are formed in the CMOS wafer in advance. This preliminary preparation simplifies the subsequent bonding process and reduces the complexity of integrating the two wafers while achieving high memory density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of 3D memory devices by preventing plasma-induced damage and improving the integration and density of the 3D memory device, while reducing the risk of plasma-induced damage to CMOS devices.
Implementation Method 1
using deep plasma etching with an etch stop layer to form through substrate contacts, thereby preventing plasma-induced damage to CMOS devices
Data Source
AI summary
A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact.