3D Memory Contact Vias With Etch-Stop Spacers for Precise Alignment
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming word-line contact via structures with self-aligned insulating spacers and etch-stop structures, which are crucial for the manufacturing of high-density memory arrays like NAND strings, due to limitations in etching precision and material compatibility.
Innovation Solution
A method involving the formation of an alternating stack of insulating and electrically conductive layers over a substrate, with a staircase region and retro-stepped dielectric material, where etch-stop structures and self-aligned insulating spacers are used to create vertically extending contact via structures, ensuring precise etching and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form word-line contact via structures, then manufacturing simplicity is maintained, but etching precision and alignment accuracy deteriorate
Solution Approach 1:
The patent applies preliminary action by forming insulating spacer layers and etch-stop structures before the actual contact via etching process. The insulating spacers are deposited conformally on the sidewalls of the alternating stack, and etch-stop structures are formed at specific depths, both in advance of the contact via formation. This preliminary preparation ensures precise etching boundaries and self-aligned features, resolving the contradiction between etching precision and structure complexity.
Solution Approach 2:
The patent segments the contact via formation process into multiple distinct steps: forming insulating spacers, forming etch-stop structures, performing first anisotropic etching to create via openings, performing second anisotropic etching to extend via cavities, and depositing conductive materials. This segmentation allows each step to be optimized independently for precision while maintaining overall process control, addressing the contradiction between manufacturing precision and device complexity.
2Manufacturing precision
If self-aligned insulating spacers are formed to improve alignment accuracy, then contact via alignment improves, but manufacturing process complexity increases
Solution Approach 1:
The patent implements self-service through self-aligned insulating spacers that automatically position themselves relative to the alternating stack structure. The spacers are formed by conformal deposition on the sidewalls, ensuring automatic alignment without requiring additional alignment steps or complex positioning mechanisms. This self-alignment approach improves contact via alignment accuracy while minimizing the increase in manufacturing process complexity.
Solution Approach 2:
The insulating spacers are formed in advance before the contact via etching process, serving as pre-positioned alignment references. This preliminary formation of spacers with precise thickness control (e.g., 5-20 nm) establishes the alignment framework that guides subsequent etching steps, improving alignment accuracy without requiring complex real-time adjustment mechanisms during manufacturing.
3Manufacturing precision
If etch-stop structures are introduced to enhance etching precision, then vertical profile control improves, but device structure complexity increases
Solution Approach 1:
The patent uses etch-stop structures as intermediary layers that mediate the etching process. These etch-stop layers (e.g., silicon nitride or silicon oxide with specific thicknesses) are deposited between the alternating conductive and insulating layers to provide controlled etching termination points. The etch-stop structures enable precise vertical profile control by limiting etch depth and protecting underlying layers, while their simple layered integration minimizes the increase in device structure complexity.
Solution Approach 2:
The etch-stop structures are applied locally at specific positions within the alternating stack where precise etching control is needed for contact via formation. Rather than modifying the entire structure uniformly, the etch-stop layers are strategically placed to provide local protection and depth control, improving vertical profile control where needed while maintaining simplicity in other regions of the device structure.
4Reliability
If laterally-insulated contact structures are formed to improve electrical isolation, then electrical isolation performance improves, but manufacturing process steps increase
Solution Approach 1:
The patent merges multiple functions into the insulating spacer structure: it provides lateral electrical isolation between adjacent contact vias, serves as an etch-stop reference for alignment, and acts as a protective barrier during subsequent processing steps. This merging of functions into a single integrated structure improves electrical isolation performance while minimizing the increase in manufacturing process steps compared to using separate structures for each function.
Solution Approach 2:
The laterally-insulated contact structures utilize the self-aligned insulating spacers to automatically provide electrical isolation without requiring additional isolation steps. The spacers, formed conformally on the sidewalls, self-generate the lateral insulation function, improving electrical isolation reliability while avoiding the need for separate manufacturing processes dedicated solely to isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-density three-dimensional memory devices with improved etching precision and electrical isolation, enhancing the performance and density of memory arrays by allowing for the efficient formation of word-line contact via structures.
Implementation Method 1
an etch-stop structure positioned at a second depth below the top surface of the alternating stack, wherein a sidewall of the etch-stop structure forms a portion of a sidewall of the contact via opening
Implementation Method 2
the insulating spacer laterally surrounding the contact via structure and contacting the perforated etch stop plate
Implementation Method 3
performing a first anisotropic etch process to form contact via openings vertically extending through the retro-stepped dielectric material portion and stopping on the stepped etch stop plate
Data Source
AI summary
Contact via openings are formed through a retro-stepped dielectric material portion in a three-dimensional memory device to underlying etch stop structures. The etch stop structures may include a stepped conductive or semiconductor etch stop plate overlying stepped surfaces in the staircase region. The contact via openings are extended through the etch stop structures. Alternatively, electrically conductive layers, including a topmost dummy electrically conductive layer in the staircase region, may be employed as etch stop structures. In this case, the contact via openings can be extended through the electrically conductive layers. Insulating spacers are formed at peripheral regions of the extended contact via openings. Contact via structures surrounded by the insulating spacers are formed in the extended contact via openings to a respective underlying electrically conductive layer.