3D Memory Cell Structure With Etch Stops for Process Reliability
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor memory devices is compromised due to manufacturing process-related issues, which affect the integration and performance of memory cells.
Innovation Solution
A semiconductor memory device design featuring a bit line, common source pattern, channel layer, filling insulating layer, gate stack structure, first etch stop pattern, second etch stop pattern, and memory pattern, along with a manufacturing method that includes forming a groove in a substrate and sequentially stacking etch stop layers, filling insulating layers, and forming a preliminary memory cell array to reduce stress and damage during the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are three-dimensionally arranged to improve integration, then the substrate area occupied by memory cells is decreased and degree of integration is improved, but operational reliability deteriorates due to manufacturing process issues
Solution Approach 1:
The patent divides the manufacturing process into multiple sequential steps with intermediate protective structures. The etch stop patterns and filling insulating layers segment the complex 3D structure formation into manageable stages, allowing precise control over each layer while maintaining overall reliability.
Solution Approach 2:
The patent forms etch stop patterns and filling insulating layers in advance before completing the full 3D structure. These preliminary protective structures are prepared to prevent damage during subsequent manufacturing steps, ensuring reliability is maintained throughout the process.
2Reliability
If multiple etch stop layers and filling insulating layers are stacked to protect the channel layer, then stress and damage during manufacturing are reduced, but device structure becomes more complex
Solution Approach 1:
The etch stop patterns and filling insulating layers act as intermediary protective structures between the bit line/common source pattern and the channel layer. These intermediaries prevent direct stress transmission and damage during manufacturing, protecting the critical channel layer while maintaining a systematic structure.
Solution Approach 2:
The patent places etch stop patterns and filling insulating layers beforehand to cushion and absorb manufacturing-induced stress. These protective structures are positioned in advance to prevent damage to the channel layer during subsequent processing steps, ensuring reliability without requiring post-manufacturing repairs.
Data Source
AI summary
A semiconductor memory device includes a bit line, a common source pattern above the bit line, a channel layer in contact with the common source pattern, the channel layer extending toward the bit line, and a filling insulating layer disposed between the bit line and the common source pattern, the filling insulating layer surrounding a first part of the channel layer. The semiconductor memory device also includes a gate stack structure disposed between the bit line and the filling insulating layer, the gate stack structure surrounding a second part of the channel layer. The semiconductor memory device further includes a first etch stop pattern on a sidewall of the filling insulating layer, a second etch stop pattern between the first etch stop pattern and the filling insulating layer, and a memory pattern between the gate stack structure and the channel layer.