3D Semiconductor Memory Device Vertical Stack Etching Protection
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Solution Overview
Problem
Current 2-dimensional memory devices have limited capacity and efficiency due to their planar structure, necessitating a transition to 3-dimensional semiconductor memory devices with vertically stacked mold and sacrificial layers to enhance storage density and operational uniformity.
Innovation Solution
A method for manufacturing a 3-dimensional semiconductor device involving the formation of vertically penetrating mold layers, sacrificial layers, protective layers, and plugging layers, with specific etching processes to create recess regions and expose conductive patterns, ensuring uniformity and preventing etching damage to the plugging layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2-dimensional planar memory structure is used, then manufacturing process is simple, but storage capacity is limited
Solution Approach 1:
The patent transitions from a 2-dimensional planar memory structure to a 3-dimensional vertically stacked structure. Multiple mold layers (first mold layer, second mold layer) are stacked vertically with sacrificial layers between them, creating vertical cavities that accommodate memory cells in three dimensions, thereby significantly increasing storage capacity while maintaining a compact footprint
2Quantity of substance
If vertically stacked mold layers are formed to increase capacity, then storage density improves, but etching damage to plugging layer increases
Solution Approach 1:
A protective layer is formed on the plugging layer before etching the sacrificial layer. This protective layer acts as a barrier during the etching process, preventing the etchant from damaging the plugging layer. The protective layer is removed after the etching is complete, having served its protective function throughout the critical etching step
Solution Approach 2:
The protective layer serves as an intermediary element between the etching process and the plugging layer. It mediates the interaction by providing a sacrificial barrier that protects the plugging layer from direct exposure to the etchant, allowing the etching to proceed safely to create the vertical cavities
3Ease of manufacture
If sacrificial layer is removed to form vertical cavities, then memory cell formation is enabled, but uniformity of structure decreases
Solution Approach 1:
The plugging layer is formed to fill the sacrificial layers before they are removed. This preliminary action ensures that when the sacrificial layers are subsequently removed to create vertical cavities, the plugging layer remains in place to maintain structural integrity and uniformity. The plugging layer acts as a template that ensures consistent cavity formation across the memory device
Solution Approach 2:
The protective layer is formed beforehand to cushion and protect the plugging layer during the sacrificial layer removal process. This preliminary protective measure ensures that the plugging layer is not damaged during etching, maintaining the uniformity and precision of the vertical cavity structure
Data Source
AI summary
Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.