3D Memory Stack Intermediate Layer for Precise Hole Etching
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Solution Overview
Problem
In three-dimensional semiconductor memory devices, achieving high shape and dimensional controllability during the etching process for memory holes and slits is challenging due to alignment shifts and variations in the stacked layers, leading to potential fluctuations in memory cell characteristics.
Innovation Solution
The introduction of a first intermediate layer made of a material with lower etching rates than the electrode and insulating layers, such as tungsten silicide, which acts as an etching stopper and helps maintain the aspect ratio of holes and slits, allowing for precise patterning across multiple stacked units, thereby controlling the configuration and dimensions of columnar portions and insulating separation films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If RIE etching is used to form memory holes and slits in stacked bodies, then high shape controllability and dimensional controllability are achieved, but alignment shifts and variations in stacked layers cause fluctuations in memory cell characteristics
Solution Approach 1:
A first intermediate layer made of tungsten silicide is introduced between the stacked units. This intermediate layer serves as an etching stopper with lower etching rates compared to the electrode and insulating layers, preventing excessive etching and maintaining the aspect ratio of holes and slits during the RIE process, thereby improving both shape controllability and memory cell characteristic uniformity
Solution Approach 2:
The patent changes the material composition and etching rate parameters by introducing tungsten silicide as an intermediate layer. This material has specifically lower etching rates than the surrounding electrode and insulating layers, allowing precise control of etching depth and maintaining consistent aspect ratios across multiple stacked units, which reduces variability in memory cell characteristics
2Productivity
If multiple stacked units are used to increase memory capacity, then device functionality is improved, but maintaining consistent aspect ratio and dimensions across stacks becomes more difficult
Solution Approach 1:
The stacked body is divided into multiple stacked units with a first intermediate layer positioned between them. This segmentation allows each unit to be etched independently while the intermediate layer ensures consistent aspect ratios across all units by acting as an etching stopper, enabling increased memory capacity while maintaining manufacturing precision
Solution Approach 2:
The first intermediate layer of tungsten silicide acts as a mediator between stacked units during the etching process. Its lower etching rate ensures that holes and slits maintain consistent aspect ratios across multiple stacked units, allowing the device to achieve higher memory capacity without sacrificing dimensional consistency
3Ease of manufacture
If etching is performed through multiple stacked layers, then memory holes and slits are formed, but variations in layer thickness and material properties cause dimensional variations
Solution Approach 1:
The first intermediate layer serves as an etching stopper that compensates for variations in layer thickness and material properties. By having a material with lower etching rates (tungsten silicide) positioned between stacked units, the etching process can proceed through multiple layers while maintaining dimensional controllability and reducing variations caused by layer inconsistencies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the controllability and precision of hole and slit formation, reducing characteristic fluctuations in memory cells and maintaining the aspect ratio, thus improving the reliability and performance of the semiconductor memory device.
Implementation Method 1
a first intermediate layer made of a material with lower etching rates than the electrode and insulating layers, such as tungsten silicide, which acts as an etching stopper
Data Source
AI summary
According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.


