3D Nonvolatile Memory Layout With Extension Regions for Dense Routing
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in increasing data storage capacity while maintaining high performance and low costs, as their integration density is limited by the area occupied by unit memory cells, which requires expensive micronizing technologies, prompting the need for three-dimensional memory solutions.
Innovation Solution
The development of a nonvolatile memory device with an extension region channel structure and plate common source line contact, along with input/output metal contacts, to efficiently utilize space and improve manufacturing process efficiency, allowing for a reduced chip size and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar nonvolatile memory device structure is used, then manufacturing process is simpler, but integration density and data storage capacity are limited
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional structure by introducing vertical stacking of memory cells, source lines, and bit lines. The memory cell strings extend in the third direction (vertical), and source lines are stacked above and below the cell region, effectively utilizing three-dimensional space to increase integration density while maintaining manufacturing feasibility through extended formation processes.
2Manufacturing precision
If ultra-expensive equipment is used for pattern micronizing, then degree of integration increases, but production cost increases significantly
Solution Approach 1:
The patent segments the memory device into distinct functional regions: a memory cell region with vertically stacked cell strings, extension regions adjacent to the cell region, and separate source line regions. This segmentation allows different manufacturing approaches for different regions, using extended formation processes for the cell region that avoid the need for ultra-fine patterning equipment while maintaining high integration density.
Solution Approach 2:
By moving to three-dimensional stacking, the patent reduces the lateral footprint of each memory cell, thereby reducing the demand for ultra-fine lateral patterning. The vertical dimension compensates for reduced lateral scaling, allowing integration density to increase without requiring the most advanced (and expensive) lithography equipment.
3Quantity of substance
If three-dimensional nonvolatile memory device is implemented, then data storage capacity increases, but device structure complexity increases
Solution Approach 1:
The patent designs the extension regions to serve multiple functions: they provide additional space for forming source lines and bit lines, facilitate electrical connections between stacked layers, and enable routing of signal lines without interfering with the memory cell region. This multi-functionality reduces the need for separate dedicated structures, thereby managing complexity while supporting three-dimensional operation.
Solution Approach 2:
The device is divided into functionally distinct regions (memory cell region, extension regions, source line regions) that can be independently optimized and manufactured. This segmentation manages structural complexity by allowing each region to be designed and formed with appropriate processes, rather than requiring the entire device to be manufactured as a single complex unit.
4Quantity of substance
If chip size is reduced to increase integration density, then data storage capacity per unit area increases, but space for electrical connections becomes limited
Solution Approach 1:
The patent utilizes the vertical dimension to provide space for electrical connections. Source lines are stacked above and below the memory cell region in the third direction, and bit lines extend vertically through the structure. This vertical arrangement provides adequate connection space without increasing the lateral chip footprint, thereby maintaining high integration density while accommodating all necessary electrical interconnections.
Solution Approach 2:
The patent separates connection functions into dedicated extension regions and source line regions that are spatially distinct from the memory cell region. This segmentation allows connection structures to be formed in specific zones without encroaching on the high-density cell region, effectively allocating space for electrical connections while maximizing storage density in the cell region.
Data Source
AI summary
A nonvolatile memory device includes a plurality of metal lines extending in a first direction and stacked in a second direction crossing the first direction, a plurality of cell structures passing through the plurality of metal lines and extending in the second direction, a plurality of extension regions, a plate common source line contact connected with a common source line, extending in the first direction, and formed in least two of the plurality of extension regions that are not formed with the plurality of cell structures, and input/output metal contacts connected with an external connection pad, extending in the first direction, and formed with at least two of the plurality of extension regions that are not formed with the plate common source line contact.