3D Memory Stack Failover Using Switchable TSV Bypass
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Solution Overview
Problem
The likelihood of a defective die adversely affecting a three-dimensional stack DRAM (3DS DRAM) device increases with the number of devices in the stack, leading to potential failures in drive and receive circuitry, which can reduce data transfer rates and increase complexity.
Innovation Solution
A three-dimensional stack DRAM (3DS DRAM) device design that incorporates switchable connections and through-silicon vias (TSVs) to bypass defective drive and receive circuitry, allowing alternative dies to take over data communication, and includes built-in self-test (BIST) for fault detection and redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of devices in the stack is increased to improve storage capacity, then storage capacity is improved, but the likelihood of defective dies increases
Solution Approach 1:
The memory system is divided into multiple independent dies (first die, second die, third die) stacked vertically. Each die can be independently tested and activated, allowing the system to segment the failure risk across multiple units rather than having a single point of failure.
Solution Approach 2:
The system dynamically changes the operational state of different dies based on test results. When a die is found to be defective, the system changes parameters by disabling that die and activating an alternative die, thereby adapting the system configuration to maintain reliability while preserving storage capacity.
2Reliability
If drive or receive circuitry fails in a stacked die, then data transfer reliability deteriorates, but adding switchable connections and alternative dies increases device complexity
Solution Approach 1:
The system employs dynamic switching capability where connections between dies can be reconfigured based on operational needs and failure conditions. The switchable connections allow the system to dynamically change data paths, enabling alternative dies to take over when primary circuitry fails, thus maintaining reliability through adaptive reconfiguration.
Solution Approach 2:
The memory controller acts as an intermediary that manages communication between the host system and multiple dies. It coordinates the switching between alternative dies, handles the complexity of managing multiple data paths, and presents a unified interface to the host, thereby isolating the complexity from the external system.
3Reliability
If built-in self-test (BIST) is implemented for fault detection, then reliability is improved, but device complexity and manufacturing complexity increase
Solution Approach 1:
The system performs preliminary testing of alternative dies before they are needed. The memory controller tests alternative dies in advance and determines their operational status, so that when a primary die fails, a pre-validated alternative is already ready to take over. This preliminary action reduces the complexity of real-time fault response.
Solution Approach 2:
The memory system performs self-diagnosis through built-in self-test (BIST) circuitry that can autonomously detect defects in dies and circuitry. This self-service capability allows the system to identify and respond to failures without external intervention, improving reliability while containing the added complexity within the memory device itself.
Data Source
AI summary
Described are memory systems and devices in which each memory die in a three-dimensional stack of memory dies includes drive and receive circuitry that can communicate data signals from the stack on behalf of all the memory dies in the stack. The drive and receive circuitry, if defective on one device in the stack, can be disabled and substituted with the drive and receive circuitry from another. The stack of memory dies can thus function despite a failure of drive or receive circuitry in one or more of the memory dies. Each memory die includes test circuitry to detect defective drive and receive circuitry.