3D Memory Failure Analysis System with Layered View Switching
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Solution Overview
Problem
The complexity of semiconductor devices with three-dimensional structures makes failure analysis challenging due to the difficulty in displaying and identifying failure modes and layers effectively, leading to increased time and risk of missing target failures.
Innovation Solution
A semiconductor device failure analysis system that generates and displays fail bit map (FBM) data by converting logical addresses to physical addresses, allowing initial display of specific layers or failure modes, and enabling efficient switching between two-dimensional and three-dimensional views to accelerate the analysis process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all layers and failure modes are displayed in an overlapped manner, then comprehensive failure analysis is achieved, but display complexity and analysis time increase significantly
Solution Approach 1:
The patent segments the complex failure analysis display into multiple independent view modes: initial display showing only critical layers/failure modes, and detailed display showing all layers/failure modes in overlapped manner. This segmentation allows users to switch between simplified and comprehensive views, reducing display complexity while maintaining the ability to perform complete failure analysis when needed.
Solution Approach 2:
The patent implements dynamic display switching that adapts to different analysis stages. The display mode changes from static comprehensive overlay to dynamic selective display based on user interaction and analysis progress, allowing the system to adjust between showing all data and showing only relevant data to reduce complexity.
2Measurement precision
If comprehensive FBM data of all layers is displayed, then complete failure information is provided, but analysis time increases and critical failures may be missed
Solution Approach 1:
The patent extracts and prioritizes critical failure information from the complete FBM data set. The initial display extracts only the most important layers and failure modes, separating them from less critical data. This extraction allows rapid identification of critical failures without requiring analysis of all comprehensive data, significantly reducing analysis time while maintaining detection of important failures.
Solution Approach 2:
The patent performs preliminary processing of FBM data to identify and prioritize critical failures before display. By pre-processing the data to determine which layers and failure modes are most critical, the system prepares the information in advance for rapid initial display, eliminating the need to process and display all comprehensive data before analysis can begin.
3Measurement precision
If detailed conversion of logical addresses to physical addresses is performed for all data, then precise failure localization is achieved, but processing time increases
Solution Approach 1:
The patent applies partial address conversion by performing logical-to-physical address conversion only on critical failure data for initial display, rather than converting all FBM data. This partial action provides sufficient localization precision for critical failures while avoiding the excessive processing time that would result from converting complete comprehensive data sets.
Data Source
AI summary
A semiconductor device failure analysis system according to an embodiment of the present invention includes a memory configured to be capable of retaining an initial display information; and a control unit configured to generate a first image based on a configuration information of the semiconductor device and a plurality of fail bit information of the semiconductor device, the semiconductor device including a three-dimensional memory cell array, and to generate a second image from the first image based on the initial display information, the second image corresponding to part of the plurality of fail bit information. The semiconductor device failure analysis system according to the embodiment further includes a display configured to be capable of initially displaying the second image.