3D Memory Word Line Fan-Out Without Staircase Structures
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Solution Overview
Problem
Planar memory cells face density limitations as feature sizes approach a lower limit, making scaling and fabrication challenging and costly, while 3D memory architectures can address these issues.
Innovation Solution
A method for forming 3D memory devices involves forming a stack structure with interleaved dielectric and conductive layers, replacing select dielectric layers with conductive layers, and creating word line pick-up structures at different depths to achieve word line pick-up/fan-out functions without staircase structures, simplifying the manufacturing process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Memory cells are arranged in vertical stacks extending through the substrate, with multiple active layers at different depths. This dimensional change allows continued density improvement without requiring further scaling of individual planar features, thereby avoiding the associated manufacturing complexity and cost increases.
2Quantity of substance
If 3D memory architecture is implemented, then memory density is improved, but device structure complexity increases
Solution Approach 1:
The 3D memory structure is segmented into multiple functional layers stacked vertically: active memory cell layers, interlayer dielectric layers, word line layers, and bit line layers. Each layer has a specific function, and the segmentation allows for modular fabrication processes. Dummy structures are also segmented and placed in non-active regions to maintain structural integrity without adding functional complexity.
Solution Approach 2:
The stacked architecture uses universal layer structures that serve multiple purposes. For example, the interleaved dielectric and conductive layers form both the memory cell structure and the word line interconnect structure. The same fabrication processes form both functional memory elements and supporting infrastructure, reducing overall device complexity.
3Reliability
If staircase structures are used for word line pick-up, then electrical connection is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent extracts and eliminates the staircase structure from the fabrication process. Instead of forming stepped terraces to access word lines at different depths, the invention uses direct vertical vias through the interlayer dielectric to reach conductive layers. This extraction of the staircase structure simplifies the manufacturing process while maintaining reliable electrical connections to word lines at all depths.
Data Source
AI summary
In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.