3D Memory Device Ferroelectric Lining Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating high-density memory components while maintaining performance and reducing parasitic capacitance, energy consumption, and manufacturing complexity.
Innovation Solution
The integration of three-dimensional memory devices with ferroelectric material, involving the formation of layer stacks over a substrate, lining openings with ferroelectric material, and forming gate electrodes, which reduces parasitic capacitance and enhances memory cell efficiency through the use of inner spacers and efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar memory structures are used, then manufacturing processes are simpler, but integration density and storage capacity are limited
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertically stacked memory cells. Multiple memory layers are stacked above each other, with bit lines extending vertically through the substrate to connect to memory cells in different layers. This dimensional change dramatically increases integration density while maintaining manufacturability through established semiconductor fabrication processes.
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but parasitic capacitance and manufacturing difficulty increase
Solution Approach 1:
The patent employs selective doping regions with different electrical characteristics in specific locations. N-type and P-type doped regions are strategically placed to create favorable electrical conditions locally, reducing parasitic capacitance at critical interfaces while maintaining high integration density. The bit line structures are also optimized with specific materials and geometries to minimize parasitic effects.
3Quantity of substance
If off-chip memory is used, then memory capacity can be increased, but access time and energy consumption increase
Solution Approach 1:
The patent integrates memory functions directly into the semiconductor chip by forming three-dimensional memory cells within the substrate itself. The bit lines extend vertically to access memory cells in multiple layers stacked on-chip, eliminating the need for separate off-chip memory components. This integration reduces access time and energy consumption while providing high memory capacity through the vertical stacking architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-density memory arrays with reduced energy consumption, faster operation, and lower manufacturing costs, while avoiding issues related to off-chip memory access, enabling smaller, cheaper, and more efficient semiconductor devices.
Implementation Method 1
lining sidewalls of the openings with a ferroelectric material
Data Source
AI summary
A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extends through the first layer stack and the second layer stack, where the openings includes first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.