3D Semiconductor Memory Stack With Ferroelectric Charge Retention

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing two-dimensional semiconductor devices face limitations in integration due to the need for expensive processing equipment to form fine patterns, which hinders the increase in data storage capacity and reliability.

Innovation Solution

A three-dimensional semiconductor memory device with a stacked structure incorporating a charge storage layer, a ferroelectric layer, and an internal insulating layer, where the internal insulating layer includes a material with a greater band gap than the charge storage and ferroelectric layers, enhancing data storage reliability and reducing operating voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If two-dimensional or planar semiconductor devices are highly integrated to increase data storage capacity, then data storage capacity is improved, but expensive processing equipment is needed to form fine patterns which increases manufacturing cost and limits further integration

Engineering Contradiction:

Improvedata storage capacityVSAvoidmanufacturing cost

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, allowing data storage capacity to increase without requiring finer lateral patterning. This dimensional change enables continued scaling of storage capacity while avoiding the need for increasingly expensive lithography equipment.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Use of energy by moving object

If the internal insulating layer uses conventional materials, then manufacturing is simpler, but operating voltage remains high and power consumption increases

Engineering Contradiction:

Improvepower consumptionVSAvoidmaterial selection complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent changes the material parameter of the internal insulating layer from conventional materials to high-k dielectric materials. This parameter change increases the dielectric constant, which enhances charge storage capability and reduces the operating voltage required for memory operations, thereby reducing power consumption.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The internal insulating layer is formed using composite material structures including high-k dielectric materials combined with other functional layers. This composite approach optimizes both electrical performance (lower operating voltage) and manufacturing feasibility.

Inventive Principle:

Principle #40Composite materials

3Reliability

If the band gap of the internal insulating layer material is increased to reduce charge leakage, then data storage reliability is improved, but the material selection becomes more restricted

Engineering Contradiction:

Improvedata storage reliabilityVSAvoidmaterial selection flexibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent selects internal insulating layer materials based on their band gap parameter, choosing materials with sufficiently large band gaps (greater than charge storage layer and ferroelectric layer) to minimize charge leakage. This parameter-based selection ensures data storage reliability while maintaining reasonable material selection flexibility.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution improves data storage reliability and reduces power consumption by minimizing the operating voltage and maintaining a wide memory window, while allowing for increased integration and data storage capacity.

Implementation Method 1

the internal insulating layer includes at least one of a first material having a greater band gap than each of the charge storage layer and the ferroelectric layer

Methodology Applied

Scientific EffectBand gap:

Implementation Method 2

a second material that is a high-k dielectric

Methodology Applied

Scientific EffectHigh-k dielectric: Dielectric

Implementation Method 3

a ferroelectric layer between the charge storage layer and the semiconductor pattern

Methodology Applied

Scientific EffectFerroelectricity:

Data Source

PatentUS20250254883A1Three-dimensional semiconductor memory device and electronic system including the same

Publication Date: 2025.08.07 SAMSUNG ELECTRONICS CO LTD

AI summary

A three-dimensional semiconductor memory device includes a substrate, a stacked structure including gate electrodes stacked on the substrate in a first direction perpendicular to a lower surface of the substrate, a semiconductor pattern penetrating the stacked structure and extending in the first direction, and a data storage pattern penetrating the stacked structure and extending in the first direction between the stacked structure and the semiconductor pattern, wherein the data storage pattern includes a charge storage layer between the gate electrodes and the semiconductor pattern, a ferroelectric layer between the charge storage layer and the semiconductor pattern, and an internal insulating layer between the charge storage layer and the ferroelectric layer, and the internal insulating layer includes at least one of a first material having a greater band gap than each of the charge storage layer and the ferroelectric layer, and a second material that is a high-k dielectric.