3D Symmetric Virtual Memory for Variable-Size FFT Architectures
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Solution Overview
Problem
Variable-size Fast Fourier Transform (FFT) architectures face challenges with high memory usage and low throughput, which can bottleneck LTE communication schemes, especially when current implementations rely on dual processing cores and double dual port memory configurations like ping-pong buffers that increase memory requirements.
Innovation Solution
The implementation of a 3D symmetric virtual memory buffer system with a dynamically reconfigurable address generator circuit, allowing data to be written and read in specific coordinate sequences, reduces memory usage while increasing throughput by optimizing data storage and retrieval in variable-length FFT computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual processing cores and double dual port memory configurations are used, then throughput requirements are met, but memory requirements increase
Solution Approach 1:
The patent applies 3D memory mapping to transform the traditional 2D memory access pattern into a three-dimensional coordinate system (x, y, z). This dimensional transformation enables more efficient memory utilization by organizing data access in three dimensions, allowing the single-port memory to achieve throughput equivalent to dual-port memory configurations without increasing physical memory capacity.
Solution Approach 2:
The patent implements dynamic reconfiguration of the memory address generator circuitry that can adaptively change the 3D memory mapping parameters and access patterns based on the specific FFT computation requirements. This dynamic adaptation allows the system to optimize memory usage for different FFT sizes and stages, achieving high throughput with a single memory port by dynamically adjusting the memory access strategy rather than relying on static dual-port architecture.
2Adaptability or versatility
If variable-size FFT computations are performed, then adaptability is improved, but memory access complexity increases
Solution Approach 1:
The patent creates a universal 3D memory mapping framework that can handle variable-size FFT computations through a single unified address generation mechanism. The 3D symmetric virtual memory structure provides a universal interface that adapts to different FFT sizes (power of 2 from 16 to 2048 points) without requiring separate memory architectures, thereby managing complexity through standardization rather than proliferation of specialized components.
Solution Approach 2:
The patent utilizes parameter changes in the 3D memory mapping configuration to accommodate variable FFT sizes. By dynamically adjusting the mapping parameters (block size, sub-block size, and dimension allocations) based on the desired FFT length, the system achieves adaptability for different computation sizes while maintaining a consistent underlying memory structure, thus avoiding the complexity of redesigning memory access for each FFT size.
3Quantity of substance
If 3D symmetric virtual memory mapping is implemented, then memory usage is reduced, but address generation complexity increases
Solution Approach 1:
The patent replaces complex software-based address generation with dedicated hardware circuitry implemented in an FPGA. The address generator is synthesized as fixed logic that directly computes 3D memory addresses from iteration variables, eliminating the need for software table lookups or complex computational routines. This hardware substitution reduces the practical complexity despite the sophisticated 3D mapping algorithm, as the logic is compiled into efficient circuitry.
Solution Approach 2:
The 3D memory mapping system is designed to be self-managing through automatic address computation based on current iteration variables. The address generator circuitry automatically translates logical (x, y, z) coordinates into physical memory addresses without requiring external intervention or complex control logic, allowing the system to manage its own memory access patterns efficiently through built-in address generation capabilities.
Data Source
AI summary
Systems and methods are disclosed for reducing memory usage and increasing the throughput in variable-size Fast Fourier Transform (FFT) architectures. In particular, 3D symmetric virtual memory is disclosed to exploit the structure inherent in variable-size FFT computations. Data samples may be written to and read from the 3D symmetric virtual memory in a specific sequence of coordinates that exploits the structure inherent in variable-size FFT computations. Memory locations in the 3D symmetric virtual memory may be mapped to memory address in a 1D buffer using an address generation circuit.