3D Memory Film Segmentation for Charge Migration Isolation
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Solution Overview
Problem
As feature sizes of semiconductor devices approach their limits, planar semiconductor fabrication techniques become challenging and costly, and three-dimensional (3D) semiconductor device architecture is needed to address density limitations, but charge lateral migration issues hinder performance in 3D NAND memory devices.
Innovation Solution
A 3D memory device structure is developed with a stack of interleaved conductive and dielectric layers, where the memory film is divided into isolated sections by dielectric layers, including a tunneling layer, storage layer, and blocking layer, to prevent charge migration, and a method for forming this structure involves forming channel holes, depositing layers, and separating them to isolate charge storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar semiconductor fabrication techniques are used to improve device density, then manufacturing cost and process complexity increase, but three-dimensional architecture introduces charge lateral migration issues
Solution Approach 1:
The memory film is segmented into multiple isolated sections along the channel length direction, with each section corresponding to a specific word line. Dielectric layers are inserted between adjacent memory film sections to physically isolate charge storage regions, preventing charge lateral migration between different word lines while maintaining high device density through vertical stacking
Solution Approach 2:
Different regions of the memory device are assigned different functional properties: the memory film in each section has charge storage capability localized to its specific word line region, while dielectric layers provide electrical isolation in between. This local differentiation of properties enables charge confinement without sacrificing overall device density
2Reliability
If memory film sections are isolated by dielectric layers to prevent charge migration, then manufacturing process complexity increases
Solution Approach 1:
Dielectric layers are formed between memory film sections during the initial stack structure fabrication process, before the memory film is fully deposited and patterned. This preliminary placement of dielectric layers simplifies subsequent processing by pre-establishing isolation regions, avoiding the need for complex post-deposition etching or isolation steps
Solution Approach 2:
The dielectric layers are integrated within the vertical stack structure, nested between the memory film sections along the channel length. This nested arrangement allows isolation functionality to be incorporated without adding lateral footprint or significantly increasing process steps, as the dielectric layers utilize the same vertical space already allocated for memory film deposition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D memory device effectively isolates charge storage across different word lines, reducing charge migration and enhancing performance by dividing the memory film into inconsecutive sections, thereby improving storage efficiency and reducing operational challenges.
Implementation Method 1
The memory film includes a tunneling layer over the semiconductor channel
Data Source
AI summary
A three-dimensional (3D) memory device includes a stack structure and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers. The channel structure extends through the stack structure along a first direction. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. The blocking layer and the storage layer are separated by the dielectric layers into a plurality of sections.