3D Memory Logic Die Layout With Fin and Planar FET Integration
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Solution Overview
Problem
Current semiconductor technologies face challenges in integrating efficient three-dimensional memory arrays with peripheral circuits that include both fin and planar field effect transistors, requiring innovative manufacturing methods to achieve compact and high-density semiconductor structures.
Innovation Solution
A semiconductor structure comprising a logic die with a word line switching circuit containing fin field effect transistors and a memory die with a three-dimensional memory device, where the method involves forming semiconductor fins, dielectric isolation layers, gate electrodes, and planar field effect transistors, and bonding these components to create a compact and efficient memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If three-dimensional memory arrays are integrated with peripheral circuits containing both fin and planar field effect transistors, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The semiconductor structure is divided into distinct first and second device regions, each optimized for specific transistor types. The first device region contains fins for fin field effect transistors while the second device region contains active semiconductor regions for planar field effect transistors, allowing independent optimization and simplifying manufacturing processes for each segment.
Solution Approach 2:
Different structural configurations are applied to different regions of the semiconductor substrate. The first device region receives vertically extending fins with specific gate dielectric and gate electrode structures, while the second device region receives laterally extending active semiconductor regions with different gate structures, enabling each region to have optimal local properties for its intended transistor type.
2Quantity of substance
If fin field effect transistors are used in the word line switching circuit, then device density is improved, but manufacturing precision requirements increase
Solution Approach 1:
Semiconductor fins are formed in the first device region before the formation of gate dielectrics and gate electrodes. This preliminary structuring establishes a robust foundation that guides subsequent manufacturing steps, ensuring consistent fin dimensions and positions that meet precise manufacturing requirements while enabling high device density.
Solution Approach 2:
The gate dielectric and gate electrode structures are formed nested around the pre-formed semiconductor fins. The gate dielectric layer is deposited conformally on the fin surfaces, and the gate electrode is formed within the gate dielectric structure, creating a nested configuration that maintains precise dimensional relationships and simplifies manufacturing control.
Data Source
AI summary
A semiconductor structure includes a logic die containing a word line switching circuit containing a fin field effect transistor having at least one semiconductor fin, and a planar field effect transistor, and a memory die containing a three-dimensional memory device bonded to the logic die.