3D Memory Cell Word Line Structure to Suppress Floating Body Effect

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Solution Overview

Problem

Existing 3D semiconductor memory devices suffer from parasitic bipolar transistor turn-on due to the floating body effect, leading to deteriorated static and dynamic refresh characteristics.

Innovation Solution

The integration of p-type field-effect transistors (pFETs) in the semiconductor memory device structure, which suppresses the floating body effect by reducing gate-induced drain leakage current and lowering bipolar gain, thereby improving electrical properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If n-type field-effect transistors (nFETs) are used in 3D semiconductor memory devices, then manufacturing is easier and device structure is simpler, but parasitic bipolar transistor turns on due to floating body effect leading to deteriorated electrical characteristics

Engineering Contradiction:

Improveelectrical characteristicsVSAvoiddevice structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the transistor type from nFET to pFET, which fundamentally alters the electrical parameters and carrier behavior. This parameter change suppresses the floating body effect and parasitic bipolar transistor turn-on, thereby improving electrical characteristics while maintaining the 3D vertical structure.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent converts the harmful floating body effect into a beneficial configuration by using pFETs where the body effect naturally suppresses parasitic bipolar transistor turn-on. The previously harmful phenomenon is transformed into a design feature that improves device reliability.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Reliability

If p-type field-effect transistors (pFETs) are integrated to suppress floating body effect, then electrical performance is improved, but device structure and manufacturing process become more complex

Engineering Contradiction:

Improveelectrical performanceVSAvoidmanufacturing process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies parameter changes by switching from nFET to pFET technology, which changes the doping type and carrier behavior. This parameter change improves electrical performance by suppressing the floating body effect, despite the increased manufacturing complexity associated with p-type device fabrication.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250386488A1Integrated circuit memory devices having high degrees of vertical integration and improved electrical characteristics

Publication Date: 2025.12.18 SAMSUNG ELECTRONICS CO LTD

AI summary

An integrated circuit memory device includes a semiconductor pattern including a first source/drain impurity region, a second source/drain impurity region and a channel region extending in series between the first and second source/drain impurity regions. A dual work function word line is provided, which includes a first material having a first work function on a first portion of the channel region, and a second material having a second work function greater than the first work function on at least a second portion of the channel region. A bit line is electrically connected to the first source/drain impurity region, and a first node of a memory cell storage device is electrically connected to the second source/drain impurity region. The first and second source/drain impurity regions may be net P-type impurity regions.