3D Memory Blocking Dielectric Layers for Fluorine Barrier Growth
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Solution Overview
Problem
Current three-dimensional memory structures face challenges in effectively forming crystalline and amorphous blocking dielectric layers, which are crucial for efficient charge storage and leakage prevention in NAND string memory devices.
Innovation Solution
A method involving the formation of an alternating stack of insulating and sacrificial layers, followed by the creation of memory openings and fill structures with crystalline blocking dielectric metal oxide layers, and the use of an amorphous dielectric nucleation layer to facilitate the growth of a crystalline metallic liner, enhancing the structural integrity and fluorine blocking properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a crystalline blocking dielectric layer is formed directly on the substrate, then charge storage capability is improved, but manufacturing complexity increases due to difficulty in forming uniform crystalline structures
Solution Approach 1:
An amorphous dielectric nucleation layer is formed first on the substrate before depositing the crystalline blocking dielectric layer. This preliminary amorphous layer serves as a nucleation site that facilitates subsequent crystallization, making the formation of uniform crystalline structures easier and more reliable.
Solution Approach 2:
The amorphous dielectric nucleation layer acts as an intermediary between the substrate and the crystalline blocking dielectric layer. It mediates the crystallization process by providing a suitable interface that promotes uniform nucleation and growth of the crystalline structure, thereby reducing manufacturing complexity while maintaining charge storage capability.
2Volume of moving object
If the amorphous dielectric nucleation layer volume is minimized, then device density is improved, but the crystalline liner formation may be compromised
Solution Approach 1:
The thickness and composition parameters of the amorphous dielectric nucleation layer are optimized to achieve the minimum necessary volume. By carefully controlling these parameters, the layer provides sufficient nucleation sites for crystalline liner formation while occupying minimal volume, thus improving device density without compromising crystalline structure formation.
3Manufacturing precision
If a thicker amorphous dielectric nucleation layer is used, then crystalline metallic liner uniformity is improved, but the volume occupied increases
Solution Approach 1:
The thickness of the amorphous dielectric nucleation layer is precisely controlled within an optimal range. This parameter optimization ensures sufficient uniformity in the resulting crystalline metallic liner while minimizing the volume occupied by the nucleation layer itself, balancing manufacturing precision with device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of robust crystalline metallic liners with improved uniformity and grain size, effectively blocking fluorine diffusion and enhancing the charge storage capabilities of the memory devices while minimizing the volume occupied by the nucleation layer.
Implementation Method 1
forming electrically conductive layers in remaining volumes of the backside recesses employing a nucleation process that forms a crystalline metallic liner on the amorphous dielectric nucleation layer
Implementation Method 2
effectively blocking fluorine diffusion
Data Source
AI summary
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.