3D Memory Interconnect Layout With Flush Local Contacts

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Solution Overview

Problem

The challenge in fabricating 3D memory devices is the complexity and cost associated with interconnect structures, particularly due to the different depths and materials of various local contacts, which complicates the fabrication process and increases cycle time.

Innovation Solution

The solution involves removing slit local contacts and merging metal deposition steps for channel, staircase, and peripheral local contacts, ensuring their upper ends are flush, thereby simplifying the fabrication process and reducing costs by using the same conductive material for all contacts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different materials and depths are used for various local contacts (channel, staircase, peripheral), then contact functionality is optimized, but fabrication complexity and cycle time increase

Engineering Contradiction:
Improvecontact functionalityVSAvoidfabrication complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the fabrication of channel local contact, staircase local contact, and peripheral local contact into a single deposition step. All three contact types are formed simultaneously using the same conductive material and process conditions, eliminating the need for separate fabrication steps for each contact type while maintaining their distinct functional characteristics

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs a universal deposition process that serves multiple functions: forming channel local contact, staircase local contact, and peripheral local contact all in one step. This multi-functional approach uses a single conductive material deposition to create different contact structures that serve different purposes in the memory device

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If multiple separate deposition steps are used for different local contacts, then material optimization is achieved, but process cycle time increases

Engineering Contradiction:
Improvematerial optimizationVSAvoidprocess cycle time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent implements continuous useful action by performing the deposition of conductive material for all local contacts in an uninterrupted single step. The deposition process continues simultaneously across all contact regions without interruption or reconfiguration, maximizing process efficiency and minimizing cycle time while maintaining material optimization

Inventive Principle:
Principle #20Continuity of useful action

3Ease of manufacture

If slit local contacts are removed and contacts are standardized, then fabrication cost and complexity decrease, but interconnect functionality must be maintained

Engineering Contradiction:
Improvefabrication easeVSAvoidinterconnect functionality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent extracts and removes the slit local contact structure from the interconnect architecture. By eliminating this redundant contact type, the fabrication process is simplified and costs are reduced, while the remaining contact structures (channel, staircase, peripheral) are optimized to maintain all necessary interconnect functions without requiring the slit contact

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20240114687A1Interconnect structures of three-dimensional memory devices
Publication Date: 2024.04.04 YANGTZE MEMORY TECH CO LTD
  • US20240114687A1 patent drawing
  • US20240114687A1 patent drawing
  • US20240114687A1 patent drawing

AI summary

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, a slit structure, and a staircase local contact. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The staircase local contact is above and in contact with one of the conductive layers at a staircase structure on an edge of the memory stack. Upper ends of the channel local contact, the slit structure, and the staircase local contact are flush with one another.