3D Memory Capacitor Structure With Vertical GAA Charge Storage
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down devices due to physical limitations, making it difficult to increase device density while maintaining performance, particularly in fabricating three-dimensional (3D) memory devices like gate-all-around (GAA) ferroelectric random access memory (FeRAM) and transistors.
Innovation Solution
The development of novel 3D GAA FeRAM devices and transistors involves forming stacked structures with alternating semiconductor layers, using high-k and ferroelectric materials, and employing advanced fabrication techniques such as atomic layer etching (ALE) with AI-based process control to create gate-all-around structures that enhance charge storage and current drive.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If lateral device dimensions are reduced to increase device density, then device size decreases, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar devices to three-dimensional vertically-stacked devices. Multiple memory cells are stacked vertically above a common substrate, enabling increased device density without further lateral scaling. This vertical stacking approach resolves the manufacturing complexity issue by maintaining lateral dimensions while achieving higher density through the third dimension.
Solution Approach 2:
The memory device is segmented into multiple discrete stacked layers, each representing a separate memory cell or cell array. This segmentation allows independent fabrication and integration of individual cells, simplifying the manufacturing process compared to attempting to fabricate densely packed lateral structures.
2Quantity of substance
If vertical dimension is increased to increase memory charge storage, then charge storage capacity increases, but device structure complexity increases
Solution Approach 1:
The patent implements a nested structure where conductor layers are embedded within dielectric layers, forming a vertical capacitor structure. The alternating stacking of conductor-dielectric-conductor sequences creates nested capacitive elements that increase charge storage capacity while maintaining a regular, manufacturable structure through standard deposition and etching processes.
3Quantity of substance
If three-dimensional gate-all-around structures are fabricated to enhance charge storage, then effective channel area increases, but fabrication process complexity increases
Solution Approach 1:
The patent forms sacrificial mandrel structures and spacer layers in advance of the final gate structure fabrication. These preliminary structures guide the subsequent formation of the gate-all-around configuration, enabling precise positioning and dimensional control while simplifying the overall fabrication sequence through pre-planned structural development.
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a first stack of semiconductor layers on a substrate. The first stack of semiconductor layers includes alternating first and second semiconductor strips. The method also includes removing the first semiconductor strips to form voids between the second semiconductor strips in the first stack of semiconductor layers. The method further includes depositing a dielectric structure layer and a first conductive fill material in the voids to surround the second semiconductor strips. Further, the method includes removing the second semiconductor strips to form a second set of voids, and depositing a second conductive fill material in the second sets of voids. In some embodiments, the first conductive fill material and the second conductive fill material are configured to form first and second electrodes of a capacitor.