3D Memory Cells With GaP Channels for Silicon-Compatible Storage
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Solution Overview
Problem
Existing memory technologies face challenges in achieving efficient and reliable data storage in three-dimensional memory arrays, particularly in terms of channel material performance and compatibility with silicon lattices.
Innovation Solution
The use of gallium phosphide (GaP) as channel material in transistors within vertically-stacked memory cells, which provides a large bandgap and reasonable mobility of charge carriers, enhancing data storage efficiency and compatibility with silicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional channel material is used in three-dimensional memory arrays, then manufacturing compatibility is maintained, but charge carrier mobility and bandgap performance are insufficient
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based channel material to gallium phosphide (GaP) channel material. This parameter change provides a larger bandgap and improved charge carrier mobility, enhancing data storage reliability while maintaining compatibility with existing silicon lattice structures through carefully controlled material integration processes
Solution Approach 2:
The patent employs composite material structures where GaP channel material is integrated with silicon-based components. This composite approach allows the GaP to provide superior electrical properties (larger bandgap, better mobility) while the silicon lattice provides structural support and manufacturing compatibility, resolving the contradiction between performance and ease of manufacture
2Productivity
If vertically-stacked memory cell structure is implemented, then storage density is improved, but channel material performance limitations become more pronounced
Solution Approach 1:
The patent addresses the performance limitations in vertically-stacked structures by changing the channel material parameters to GaP, which has superior charge carrier mobility and larger bandgap. These parameter changes directly improve electron transport efficiency in the vertical channel, enabling high-density three-dimensional stacking while maintaining reliable device operation
3Reliability
If larger bandgap material is used, then charge carrier mobility improves, but integration with existing silicon-based processes becomes more difficult
Solution Approach 1:
The patent uses composite material integration where GaP channel layers are deposited within a silicon-based process flow. The GaP provides the desired large bandgap and high charge carrier mobility, while the overall structure maintains compatibility with standard silicon CMOS fabrication processes through careful control of deposition conditions and interface engineering
Solution Approach 2:
The patent employs intermediary layers and buffer structures at the interfaces between GaP and silicon components. These intermediary elements facilitate the integration of the wide-bandgap GaP material with conventional silicon processes, enabling high-mobility channel operation while maintaining ease of manufacture through standardized fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
GaP channel material improves the performance of memory cells by offering a large bandgap and suitable charge carrier mobility, leading to enhanced data storage efficiency and compatibility with silicon lattices in three-dimensional memory arrays.
Implementation Method 1
Each of the transistors has channel material with a bandgap greater than 2 electron-volts
Implementation Method 2
The capacitor may electrostatically store energy as an electric field within capacitor dielectric between two capacitor plates
Data Source
Figure 1
Figure 2~2A
Figure 3
AI summary
Some embodiments include a memory array having vertically-stacked memory cells. Each of the memory cells includes a transistor coupled with a charge-storage device, and each of the transistors has channel material with a bandgap greater than 2 electron-volts. Some embodiments include a memory array having digit lines extending along a vertical direction and wordlines extending along a horizontal direction. The memory array includes memory cells, with each of the memory cells being uniquely addressed by combination of one of the digit lines and one of the wordlines. Each of the memory cells includes a transistor which has GaP channel material. Each of the transistors has first and second source/drain regions spaced from one another by the GaP channel material. The first source/drain regions are coupled with the digit lines, and each of the memory cells includes a capacitor coupled with the second source/drain region of the associated transistor.