3D Memory Gate Structure With Barrier-Layered Conductive Layers
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the area occupied by unit memory cells, and existing three-dimensional semiconductor devices face challenges in achieving stable and reliable operation.
Innovation Solution
A semiconductor device with a gate structure comprising alternately stacked conductive layers and insulating layers, featuring channel structures and contact plugs connected to the conductive layers. Each conductive layer includes a first portion with a first thickness and a second portion with a second thickness, where the second portion includes a first metal layer, a second metal layer within the first metal layer, and a first barrier layer interposed between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in three dimensions to improve integration density, then the area occupied by unit memory cells is reduced, but the reliability and stability of device operation becomes difficult to ensure
Solution Approach 1:
The conductive layer is segmented into multiple portions (first portion, second portion, third portion) with different thicknesses and structures. Each portion serves specific functions: the first portion provides base conductivity, the second portion with increased thickness enhances electrical connection reliability, and the third portion enables contact plug formation. This segmentation allows the device to achieve both high integration density through 3D stacking and reliable operation through optimized local structures.
Solution Approach 2:
Different regions of the conductive layer are given different local qualities (thickness, material composition, barrier layer presence). The second portion has greater thickness for improved electrical connection, while the third portion is configured for contact plug formation. This local quality variation ensures that each region performs its specific function optimally, maintaining reliability while enabling 3D stacking for high integration density.
2Reliability
If a multi-layer conductive structure with barrier layers is used to improve reliability, then the manufacturing complexity increases, but the integration density benefit is reduced
Solution Approach 1:
The conductive layer is divided into multiple portions with distinct structures. The first portion provides base conductivity, the second portion with enhanced thickness improves connection reliability, and the third portion enables contact plug formation. This segmentation allows reliability to be improved through targeted structural enhancements only where needed, rather than complicating the entire conductive layer structure.
Solution Approach 2:
Barrier layers and increased thickness are applied locally only in specific portions (second and third portions) where reliability is most critical for electrical connections and contact plugs. The first portion maintains a simpler structure. This local quality approach improves device stability without unnecessarily increasing overall manufacturing complexity.
Data Source
AI summary
A semiconductor device includes a gate structure including alternately stacked conductive layers and insulating layers, channel structures passing through the gate structure. Each of the conductive layers may include a first portion having a first thickness and a second portion having a second thickness thicker than the first thickness, and the second portion may include a first metal layer, a second metal layer in the first metal layer, and a first barrier layer interposed between the first metal layer and the second metal layer.