3D Memory Gate Electrode Layout for Reliable Contact Regions
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Solution Overview
Problem
There is a need for semiconductor devices with improved reliability and increased data storage capacity, particularly in systems that require high-capacity data storage, where existing two-dimensional memory cell arrangements are insufficient.
Innovation Solution
A semiconductor device design featuring a substrate with gate electrodes of varying lengths, interlayer insulating layers, channel structures, and contact plugs that penetrate through the gate electrodes, with the gate electrodes having a decreased thickness in specific regions to enhance physical properties and reliability, allowing for increased data storage capacity and improved connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate electrodes have uniform thickness throughout, then manufacturing is simpler, but reliability is reduced due to stress concentration at contact regions
Solution Approach 1:
The gate electrode structure implements local quality by having different thicknesses in different regions: a first thickness in the channel region and a second (reduced) thickness in the contact region. This local variation reduces stress concentration at the contact region while maintaining effective gate control in the channel region, thereby improving device reliability without requiring complete structural redesign.
Solution Approach 2:
The gate electrode is segmented into multiple regions with different thicknesses along its length. The electrode is divided into a channel region portion and a contact region portion, each with optimized thickness for its specific function. This segmentation allows the structure to address multiple performance requirements simultaneously.
2Quantity of substance
If two-dimensional memory cell arrangement is used, then device structure is simpler, but data storage capacity is insufficient
Solution Approach 1:
The memory device transitions from a two-dimensional memory cell arrangement to a three-dimensional structure by stacking multiple layers of memory cells vertically. This dimensional change significantly increases the data storage capacity within the same footprint area, allowing higher density storage without proportionally increasing the device footprint.
3Reliability
If gate electrodes extend full length over second region, then connectivity is improved, but stress concentration increases at contact regions
Solution Approach 1:
The gate electrode implements local quality by reducing its thickness specifically in the contact region where stress concentration occurs, while maintaining full length extension for electrical connectivity. This localized modification addresses the stress issue without compromising the overall connectivity function.
Solution Approach 2:
Instead of reducing the gate electrode thickness uniformly throughout, the invention applies partial action by reducing thickness only in the specific contact region portion where stress concentration is problematic. This selective approach maintains adequate thickness in the channel region for proper gate control while relieving stress in the contact region.
Data Source
AI summary
A semiconductor device includes: a substrate that includes a first region and a second region; gate electrodes stacked on the first region in a first direction, extend by different lengths in a second direction on the second region, and respectively including a pad region having an upper surface that is upwardly exposed in the second region; interlayer insulating layers alternately stacked with the gate electrodes; channel structures that extend in the first direction and penetrate through the gate electrodes; plug insulating layers alternately disposed with the interlayer insulating layers and parallel to the gate electrodes below the pad region; and contact plugs that extend in the first direction and respectively penetrate through the pad region and the plug insulating layers below the pad region. In each of the gate electrodes, the pad region has physical properties that differ from physical properties of regions other than the pad region.