3D Memory Gate Contact Structure for Reliable Vertical Stacking
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and integration density while maintaining reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
A semiconductor device design featuring a stack structure with vertically stacked gate layers, memory vertical structures, and conductive gap fill patterns with liner layers, along with specific contact plug configurations to enhance electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple gate layers vertically. The stack structure includes first gate layers, second gate layers, and third gate layers positioned at different heights, enabling data storage in the vertical dimension while maintaining planar footprint.
Solution Approach 2:
The memory device is divided into multiple functional segments: stack structures containing gate layers for data storage, contact plugs for electrical connection, and interlayer insulating layers for isolation. Each segment performs a specific function, allowing independent optimization and simplifying the overall complex structure.
2Quantity of substance
If multiple gate layers are stacked vertically to improve integration density, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
Interlayer insulating layers are formed between the first gate layers, second gate layers, and third gate layers before the gate layers are stacked. This preliminary formation of insulating structures provides a stable foundation and alignment references, reducing the precision requirements for subsequent gate layer stacking operations.
Solution Approach 2:
Interlayer insulating layers serve as intermediary structures between adjacent gate layers. These insulating layers provide physical separation, electrical isolation, and mechanical support, facilitating the stacking process and reducing the precision requirements for direct gate-to-gate alignment.
3Ease of operation
If contact plugs are formed to connect gate layers electrically, then electrical connectivity is improved, but reliability challenges increase
Solution Approach 1:
The contact plug structure is formed as a nested configuration where the conductive gap fill pattern is surrounded and protected by the conductive liner layer. This nested structure provides mechanical support and electrical continuity while protecting the internal conductive material from degradation, thereby improving reliability.
Solution Approach 2:
The contact plug combines two different conductive materials: a gap fill pattern material and a liner layer material. The composite structure leverages the advantages of each material - the gap fill material provides bulk conductivity while the liner material provides interface stability and adhesion, collectively improving electrical connectivity and reliability.
Data Source
AI summary
A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.