3D Memory String Structure That Avoids Gate Insulation Etching
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Solution Overview
Problem
Conventional semiconductor storage devices face challenges in miniaturization due to increased costs and physical limitations, such as the removal of memory gate insulation layers during the diluted fluorinated acid process, which affects the formation and integration of three-dimensional memory cells.
Innovation Solution
A non-volatile semiconductor storage device with a plurality of memory strings, each comprising columnar semiconductor layers and charge storage layers, where the memory cells are formed by creating grooves and holes aligned with the ends of conductive layers, allowing for the formation of U-shaped semiconductors with hollow portions and internal insulation, enabling stable integration without the need for wet etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory gate insulation layers are formed and subjected to diluted fluorinated acid process, then columnar semiconductors can be formed to fill holes, but the memory gate insulation layers are removed by etching
Solution Approach 1:
The patent introduces a protective film as an intermediary layer between the memory gate insulation layer and the etching solution. This protective film acts as a barrier that prevents the etching solution from directly contacting and removing the memory gate insulation layer, while still allowing the etching process to proceed on the sacrificial layer. The protective film is subsequently removed to complete the process.
Solution Approach 2:
The patent applies preliminary protective action by forming the protective film before the etching process. This protective film pre-empts the harmful etching effect on the memory gate insulation layer, ensuring that the insulation layer remains intact throughout the etching process and is not accidentally removed.
2Length of moving object
If photolithography technology is improved for miniaturization, then element size is reduced to increase storage capacity, but the cost necessary for lithography process is more and more increased
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by forming columnar semiconductor structures that extend in the vertical direction. This dimensional change allows multiple memory cells to be stacked vertically, increasing storage capacity without requiring further reduction in lateral element dimensions, thereby avoiding the escalating costs of advanced photolithography.
Solution Approach 2:
The patent divides the memory structure into multiple stacked layers including alternating conductive layers and insulation layers, with columnar semiconductors formed in vertical holes through each stack. This segmentation into repeating units allows for scalable three-dimensional integration that achieves high density without requiring proportionally advanced lithography capabilities for each layer.
3Productivity
If memory cells are three-dimensionally disposed to increase degree of integration, then storage capacity is increased, but the complexity of manufacturing process is increased
Solution Approach 1:
The patent merges multiple functions into the protective film layer, which simultaneously serves as an etch barrier for the memory gate insulation layer, a structural support during processing, and a temporary placeholder that is removed later. This merging reduces the need for separate process steps and simplifies the overall manufacturing complexity despite the three-dimensional structure.
Solution Approach 2:
The patent performs preliminary formation of the protective film and sacrificial layer structure before the actual etching and columnar semiconductor formation. This preliminary action prepares the structure in advance, making the subsequent etching process simpler and more controlled, and avoiding the need for complex in-situ adjustments during the main fabrication process.
Data Source
AI summary
A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.