3D Memory Gate Extension Structure for Polarization Switching
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Solution Overview
Problem
In 3D memory devices, the large spacer and distance between drains and source inhibit the electric field from flowing effectively, leading to polarization switching issues, which can cause memory read failures due to a small memory window and hinder the transition from program mode to erase mode.
Innovation Solution
The introduction of gate extension structures that extend axially towards the source, improving the electric field across the channel layer and facilitating polarization switching by extending the gate length beyond the inner spacer, thus enhancing memory device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the spacer length and distance between drains and source are increased, then device isolation and structural stability are improved, but electric field flow is inhibited leading to polarization switching issues
Solution Approach 1:
The gate extension structure extends in the axial direction (first direction) beyond the inner spacer, adding a dimensional extension to the gate that allows electric field to reach the channel layer near the source region. This axial extension resolves the contradiction by providing a pathway for electric field flow without reducing the radial spacer dimensions that provide structural stability.
Solution Approach 2:
The gate extension structure acts as an intermediary element between the gate and the channel layer near the source. It mediates the electric field transmission by extending the gate's influence into the region between the source and inner spacer, enabling polarization switching without compromising the isolation provided by the spacer.
2Reliability
If the gate length is extended beyond the inner spacer, then polarization switching is facilitated, but device complexity increases
Solution Approach 1:
The gate structure is segmented into two distinct parts: the main gate body and the gate extension. This segmentation allows the gate extension to be optimized specifically for electric field extension without affecting the main gate's function. The extension is a simplified structure that adds functionality without proportionally increasing overall complexity.
Solution Approach 2:
The gate extension utilizes the axial dimension to provide additional functionality. By extending in the first direction rather than increasing radial dimensions, the structure achieves polarization switching enhancement with minimal impact on device footprint and manufacturing complexity.
3Reliability
If the memory window is increased, then read reliability is improved, but the small memory window caused by large spacer distance becomes a limiting factor
Solution Approach 1:
The gate extension serves as an intermediary that enhances electric field coupling between the gate and channel layer. This improved coupling increases the memory window by enabling more effective polarization switching, directly addressing the limitation imposed by the large spacer distance.
Solution Approach 2:
By extending the gate axially beyond the inner spacer, the structure creates additional overlap region between gate and channel. This dimensional extension increases the effective interaction area, thereby enlarging the memory window and improving read reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively addresses the polarization switching issues, reducing memory read failures by improving the electric field and enabling reliable transitions between program and erase modes in 3D memory devices.
Implementation Method 1
improving the electric field across the channel layer and facilitating polarization switching
Data Source
AI summary
A semiconductor device comprises a source and a pair of drains disposed on either side of the source in a first direction and spaced apart therefrom. A channel layer extending in the first direction is disposed on at least one radially outer surface of the source and the pair of drains in a second direction perpendicular to the first direction. A memory layer extending in the first direction is disposed on a radially outer surface of the channel layer in the second direction. At least one gate layer that extends in the first direction, is disposed on a radially outer surface of the memory layer in the second direction. A gate extension structure extends from the each of the drains at least part way towards the source in the first direction, and is located proximate to, and in contact with each of the channel layer and the corresponding drain.