3D Memory Gate Electrode Layout With Vertical Channel Interconnects
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Solution Overview
Problem
Current semiconductor devices face limitations in increasing data storage capacity, particularly in three-dimensional memory cell configurations, where efficient interconnection and channel structure designs are needed to enhance storage density and productivity.
Innovation Solution
A semiconductor device is designed with a stacked gate electrode structure, including first and second gate electrodes of varying thicknesses, and channel structures that penetrate through these electrodes, connected by contact plugs to circuit interconnection lines, allowing for vertical extension and electrical connectivity, thereby optimizing data storage capacity and productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed three-dimensionally to increase data storage capacity, then storage density is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertical stacking, where multiple gate electrodes (first, second, third gate electrodes) are stacked vertically above the plate layer. This dimensional change enables increased storage capacity by utilizing the vertical space above the substrate, allowing memory cells to be arranged in multiple layers rather than a single plane.
Solution Approach 2:
The gate electrodes are divided into multiple segmented layers (first gate electrode, second gate electrode, third gate electrode) stacked vertically, with channel structures penetrating through specific combinations of these segments. This segmentation allows independent control of different memory cell layers, managing the complexity of three-dimensional operations by treating each layer as a manageable unit.
2Quantity of substance
If gate electrodes are stacked vertically to enable three-dimensional memory cells, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
Channel structures are formed to penetrate through specific gate electrodes (e.g., first channel structures through first and second gate electrodes, second channel structures through second and third gate electrodes), creating a nested configuration where channels pass through multiple stacked layers. This nesting approach enables precise vertical alignment and connectivity between different memory cell layers, managing the precision requirements through systematic layer integration.
Solution Approach 2:
Different gate electrodes have different thicknesses in the vertical direction (first gate electrode with first thickness, second gate electrode with second thickness greater than first, third gate electrode with third thickness), allowing localized optimization of electrical characteristics and control for each memory cell layer. This local quality variation enables tailored performance for different vertical positions while maintaining overall device functionality.
3Reliability
If contact plugs are used to electrically connect gate electrodes to circuit interconnection lines, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The second gate electrode serves multiple functions: it acts as a control gate for memory cells in the first region, extends into the second region to provide contact surfaces, and enables common connection to multiple contact plugs. This multi-functionality reduces the need for separate connection structures for each gate electrode, simplifying the overall device architecture while maintaining reliable electrical connectivity between the vertically stacked gate electrodes and circuit interconnection lines.
Data Source
AI summary
A semiconductor device includes a first semiconductor structure including a substrate, circuit devices on the substrate, and circuit interconnection lines on the circuit devices; and a second semiconductor structure on the first semiconductor structure and having a first region and a second region, wherein the second semiconductor structure includes gate electrodes; first channel structures in the first region; second channel structures in the first region; and contact plugs in the second region, the gate electrodes include first gate electrodes having a first thickness in the vertical direction in the first region and second gate electrodes having a second thickness in the vertical direction greater than the first thickness in the first region, and the second gate electrodes are commonly connected to one of the contact plugs.