3D Memory Gate Stack Layout for Capacity and Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and reliability, particularly in three-dimensional memory cell configurations.
Innovation Solution
The semiconductor device incorporates a stacked structure with horizontal conductive layers, gate electrodes, channel structures, and isolation regions, featuring specific width variations and insulating regions to enhance data storage capacity and reliability, along with bonding metal layers for improved electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed three-dimensionally to increase data storage capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional memory cell stacking by vertically stacking multiple memory cell layers (first memory cell layer, second memory cell layer, etc.) above the substrate. This vertical arrangement transitions from two-dimensional to three-dimensional spatial utilization, thereby increasing data storage capacity while managing device complexity through systematic layering and standardized interconnection structures.
2Quantity of substance
If multiple gate electrodes are stacked vertically, then data storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The vertical gate electrode structure is segmented into multiple distinct layers (first gate electrode, second gate electrode, third gate electrode, fourth gate electrode) with clear functional differentiation. Each gate electrode layer is manufactured and patterned separately, allowing for independent process optimization and quality control. This segmentation reduces the cumulative precision requirements compared to forming a single monolithic vertical structure.
Solution Approach 2:
The patent employs preliminary patterning and formation of gate electrode layers before final assembly and connection. Each gate electrode is prepared and positioned in advance with predetermined patterns and orientations, ensuring that alignment and dimensional tolerances are established during individual layer fabrication rather than requiring perfect alignment during final assembly.
3Reliability
If insulating regions with varying widths are implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The insulating regions are designed with non-uniform width characteristics, where the first insulating region has a first width and the second insulating region has a second width different from the first. This local variation in dimensions allows for optimized electrical isolation and stress distribution in different areas of the device, improving overall reliability while maintaining a relatively simple global structural framework.
Data Source
AI summary
A semiconductor device includes gate electrodes stacked and spaced apart from each other including upper gate electrodes, memory gate electrodes and lower gate electrodes sequentially stacked from the horizontal conductive layer; a horizontal connection portion between the memory gate electrodes and the lower gate electrodes; channel structures penetrating through the gate electrodes and extending in the first direction in the first region; isolation regions penetrating through the gate electrodes; an insulating region extending from a lowermost surface of the gate electrodes and penetrating through at least one of the lower gate electrodes between the isolation regions; wherein an upper surface of the insulating region has a first width, a lower surface has a second width greater than the first width, an upper surface of each of the channel structures has a third width, and a lower surface has a fourth width smaller than the third width.