3D Memory Gate Electrode Layout for Higher Density Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity, particularly in transitioning from two-dimensional to three-dimensional memory cell arrangements.
Innovation Solution
A semiconductor device design featuring first and second memory regions with an extension region in between, incorporating word lines at different height levels and overlapping circuit regions, including common and individual transistors and gate electrodes, to enhance integration and reduce the overall plan area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional memory cell arrangement by stacking multiple memory regions (first memory region, second memory region, and extension region) vertically. Word lines are positioned at different height levels (first height level, second height level, third height level) to control memory cells in different vertical layers, enabling increased storage capacity through vertical dimension exploitation rather than horizontal expansion.
Solution Approach 2:
The memory device is divided into distinct functional segments: first memory region, second memory region, and extension region. Each region has specific word lines (first common word lines, second common word lines, intermediate individual word lines) that can be independently controlled. This segmentation allows complex three-dimensional storage to be managed through modular, region-specific control mechanisms, reducing overall system complexity.
2Quantity of substance
If word lines are disposed at different height levels to enable three-dimensional memory arrangement, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
Word lines are segmented into different height levels with specific functions: first common word lines at a first height level, second common word lines at a second height level, and intermediate individual word lines at a third height level. Each segment can be manufactured and controlled independently, allowing precise positioning in the vertical dimension while managing manufacturing complexity through modular fabrication approaches.
3Area of stationary object
If circuit region overlaps extension region in vertical direction to reduce plan area, then device area is reduced, but device complexity increases
Solution Approach 1:
The circuit region is positioned to overlap the extension region in the vertical direction rather than occupying adjacent horizontal space. This vertical stacking arrangement reduces the overall plan area of the device by utilizing the third dimension (height) for circuit placement, effectively converting a two-dimensional layout problem into a three-dimensional spatial optimization.
Solution Approach 2:
The first structure (containing memory regions and extension region) and the second structure (containing circuit region) are merged in the vertical direction, with the circuit region overlapping the extension region. This merging of structures in the vertical dimension reduces the total device footprint while integrating memory and circuit functions in a compact three-dimensional configuration.
Data Source
AI summary
A semiconductor device includes a first gate electrode, a second gate electrode disposed at a level different from the first gate electrode, a third gate electrode disposed at the same level as the second gate electrode and spaced apart from the second gate electrode, a first common pass transistor electrically connected to the first gate electrode, a first individual pass transistor electrically connected to the second gate electrode, and a second individual pass transistor electrically connected to the third gate electrode. A size of a channel region of the first common pass transistor is greater than a size of a channel region of each of the first individual pass transistor and the second individual pass transistor.