3D Memory Gate Line Structure to Prevent Block Collapse
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Solution Overview
Problem
The high aspect ratio of 3D memory devices poses challenges in manufacturing, particularly in forming channel holes and gate line holes without merging, which can lead to tilting or collapsing of memory blocks, affecting the quality and yield of the device.
Innovation Solution
A gate line structure is formed between memory blocks, comprising gate line insulating layers and pillars, to insulate conductive layers and improve structural stability, allowing channel and gate line holes to be formed in a single etching process, reducing fabrication costs and enhancing device quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel holes and gate line holes are formed in a single etching process, then manufacturing efficiency is improved and fabrication costs are reduced, but memory blocks may tilt or collapse due to high aspect ratio
Solution Approach 1:
The gate line structure is segmented into multiple components: gate line insulating layers spaced along the first direction, and pillars spaced along the second direction and extending through the gate line insulating layers. This segmentation provides distributed structural support to prevent tilting or collapsing of memory blocks while allowing single-etch formation of channel and gate line holes.
Solution Approach 2:
The gate line structure acts as an intermediary element between memory blocks, providing mechanical support and insulation. The gate line insulating layers and pillars serve as intermediate structures that prevent direct contact between conductive layers of different memory blocks, thereby preventing tilting or collapsing while enabling integrated hole formation.
2Reliability
If gate line structure with insulating layers and pillars is formed between memory blocks, then structural stability is improved and tilting or collapsing is prevented, but device complexity increases
Solution Approach 1:
The gate line structure performs multiple functions simultaneously: it provides mechanical support to prevent memory block tilting or collapsing, electrically insulates conductive layers of different memory blocks, and enables single-etch formation of channel and gate line holes. This multi-functionality reduces the need for separate structures, thereby managing complexity despite the added components.
Solution Approach 2:
The formation of channel holes and gate line holes is merged into a single etching process, reducing manufacturing steps. Additionally, the gate line structure combines insulating layers and pillars into an integrated component that simultaneously provides insulation and mechanical support, managing overall device complexity through functional integration.
Data Source
AI summary
The present disclosure relates to methods, devices, systems, and techniques for managing channel hole and gate line merging in semiconductor devices. An example semiconductor device includes a first memory block, a second memory block, and at least a first gate line structure between the first memory block and the second memory block. Each of the first memory block and the second memory block includes a stack of conductive layers and insulating layers alternating with each other along a first direction. The first gate line structure insulates the conductive layers of the first memory block from the conductive layers of the second memory block. The first gate line structure includes gate line insulating layers spaced along the first direction and pillars that are spaced along a second direction perpendicular to the first direction and extend through the gate line insulating layers along the first direction.