3D Nonvolatile Memory Gate Structure Signal Isolation
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in maintaining structural stability and signal reliability due to signal interference between neighboring memory cells, particularly as design rules decrease and integration increases, leading to issues with memory cell density and storage operation reliability.
Innovation Solution
A nonvolatile memory device with a three-dimensional structure featuring a gate structure with alternately stacked gate electrode and interlayer insulation layers, where the gate electrode protrudes into hole patterns, and functional layers are disposed along the sidewall surfaces, allowing for independent operation of memory element units and reducing signal interference through gap filling layers and channel layers that contact cell portions of the second functional layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rules are decreased and integration is increased to improve memory cell density, then memory cell density is improved, but signal interference between neighboring memory cells increases and structural stability deteriorates
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical structure. Memory element units are stacked vertically with gate electrode layers arranged in multiple levels (first through fourth gate electrode layers at different heights), enabling increased storage density without increasing lateral footprint. This vertical stacking allows neighboring cells to be spatially separated in the third dimension, reducing signal interference while maintaining high integration.
Solution Approach 2:
The memory device is divided into multiple independent memory element units (first, second, third, and fourth memory element units), each with its own gate electrode layer and functional layers. These units are segmented vertically and laterally, with insulating layers and channel layers separating them. This segmentation isolates signal paths between neighboring cells, preventing signal interference even as density increases.
2Reliability
If gate electrode layers are made to protrude into hole patterns to improve signal isolation, then signal interference is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrode layers are nested within hole patterns formed in insulating layers. Each gate electrode layer (first through fourth) is positioned within corresponding hole patterns, creating a nested structure where conductive elements are embedded in insulating matrices. This nesting provides natural lateral confinement and positioning, reducing the need for high-precision alignment while achieving effective signal isolation between adjacent memory element units.
3Reliability
If functional layers are disposed along sidewall surfaces to improve cell isolation, then signal interference is reduced, but device complexity increases
Solution Approach 1:
Functional layers (first and second functional layers) are selectively disposed along specific sidewall surfaces of memory element units where signal isolation is most critical. The first functional layer is positioned along sidewalls facing adjacent memory units, while the second functional layer is positioned at different locations. This localized placement provides effective cell isolation only where needed, rather than uniformly throughout the entire device, thereby reducing unnecessary complexity while maintaining reliability.
Data Source
AI summary
A nonvolatile memory device according to an embodiment includes a substrate, and a gate structure disposed on the substrate and including a hole pattern. The gate structure includes at least one gate electrode layer and at least one interlayer insulation layer which are alternately stacked, and the gate electrode layer protrudes toward a center of the hole pattern relative to the interlayer insulation layer. The nonvolatile memory device includes a first functional layer disposed along a sidewall surface of the gate structure inside the hole pattern, a second functional layer disposed on the first functional layer inside the hole pattern, and a channel layer extending in a direction perpendicular to the substrate inside the hole pattern and disposed to contact a cell portion of the second functional layer. The cell portion of the second functional layer indirectly covers a sidewall surface of the gate electrode layer.