3D Memory Top Select Gate Segmentation for Signal Integrity
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and increasing costs, leading to density constraints, which can be addressed by transitioning to a three-dimensional (3D) memory architecture.
Innovation Solution
A semiconductor device with a stack structure of alternating insulating layers and word line layers, featuring a top select gate (TSG) layer divided by a separation structure into sub-layers, with conductive layers positioned between these sub-layers, and channel structures extending through the stack to enhance memory density and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to a three-dimensional stacked architecture. Memory cells are arranged vertically in multiple layers with alternating insulating and word line layers, allowing density scaling without proportionally increasing fabrication complexity. This vertical stacking enables continued density improvement while maintaining process feasibility.
Solution Approach 2:
The memory array is divided into multiple independent sections separated by separation structures that extend through the stacked layers. Each section can be independently fabricated and operated, allowing complex 3D structures to be built using repeated, standardized fabrication steps rather than monolithic complex processes.
2Quantity of substance
If feature sizes of memory cells are reduced to increase density, then memory density is improved, but manufacturing cost increases
Solution Approach 1:
By stacking memory cells vertically instead of reducing lateral feature sizes, the patent achieves density improvement without the exponential cost increase associated with sub-10nm planar scaling. The vertical dimension provides a cost-effective path to higher density using existing fabrication capabilities.
Solution Approach 2:
The patent changes the scaling parameter from lateral dimension reduction to vertical layer multiplication. Instead of making individual cells smaller (which increases manufacturing difficulty), the design multiplies the number of cell layers, utilizing standard thin-film deposition and etching processes that remain cost-effective.
3Quantity of substance
If a 3D memory architecture is implemented to increase density, then memory density is improved, but voltage drop and signal delay increase
Solution Approach 1:
Conductive layers are introduced as intermediary elements between the separation structures and the memory cell components. These conductive layers provide low-resistance electrical pathways that connect word lines and select gates across multiple stacked layers, reducing voltage drop and maintaining signal integrity despite the increased vertical distance.
Solution Approach 2:
The patent extracts the voltage drop and signal delay problems from the memory cell operation by introducing dedicated conductive interconnect layers. These separate interconnect layers handle the electrical signaling function, allowing the memory cell stack to focus on storage while signal integrity is maintained through optimized conductive pathways.
4Adaptability or versatility
If separation structures are used to divide the top select gate layer into sub-layers, then independent operation of memory sections is improved, but device complexity increases
Solution Approach 1:
The top select gate layer is segmented into multiple sub-layers by separation structures that extend through the stack. This segmentation allows different sections of the memory array to be independently addressed and operated, providing versatility while using a regular, repeating structural pattern that manages complexity through standardization.
Data Source
AI summary
According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure of alternating insulating layers and word line layers, a first top select gate (TSG) layer over the stack structure, and a separation structure extending through the first TSG layer, where the first TSG layer is divided by the separation structure into a first sub TSG layer and a second sub TSG layer. The semiconductor device includes a conductive layer positioned between the first sub TSG layer and the separation structure, and between the second sub TSG layer and the separation structure.