3D Memory Gate Separation Layout for Reliable High-Density NAND
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and ensuring reliability and mass productivity, particularly in three-dimensional memory cell arrangements.
Innovation Solution
The semiconductor device incorporates a unique structure with gate electrodes, channel structures, and separation regions, including a second separation region that is self-aligned between studs, enhancing reliability and productivity by simplifying the manufacturing process and protecting channel structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacitance is improved, but manufacturing complexity and reliability challenges increase
Solution Approach 1:
The patent divides the three-dimensional memory structure into distinct functional segments: plate layer, multiple gate electrodes (lower gate, memory gates, upper gate), channel structures, and separation regions. This segmentation allows each component to be optimized and manufactured independently, reducing overall manufacturing complexity while maintaining high storage capacity
Solution Approach 2:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking by vertically arranging gate electrodes and channel structures. Multiple gate electrodes are stacked in the vertical direction with channel structures penetrating through them, enabling increased storage capacity without proportionally increasing manufacturing complexity
2Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacitance is improved, but reliability deteriorates
Solution Approach 1:
The patent introduces separation regions as intermediary structures between adjacent memory cell strings. These separation regions penetrate through the stack structure and extend in the horizontal direction, electrically isolating adjacent memory cells and preventing interference, thereby improving reliability while maintaining three-dimensional high-capacity architecture
Solution Approach 2:
The patent extracts and removes portions of the stack structure to form separation regions that extend horizontally through the memory device. By taking out material in specific locations, the patent creates electrical isolation paths that prevent signal interference between adjacent memory cells, enhancing device reliability
3Quantity of substance
If complex three-dimensional structures are used to increase storage capacity, then data storage capacity is improved, but mass productivity deteriorates
Solution Approach 1:
The patent forms separation regions and second separation regions in advance during the manufacturing process, before final device assembly. The second separation region is formed to extend through the upper gate electrode and cell region insulating layer, creating pre-defined isolation structures that simplify subsequent manufacturing steps and enable mass production
Solution Approach 2:
The separation regions and second separation regions serve multiple functions simultaneously: they provide electrical isolation between memory cells, define structural boundaries for manufacturing alignment, and facilitate mass production through standardized repeating patterns. This multi-functionality reduces the number of separate manufacturing steps required
Data Source
AI summary
A semiconductor device includes a plate layer, gate electrodes including a lower gate electrode, memory gate electrodes, and an upper gate electrode, channel structures in channel holes penetrating through the gate electrodes, a cell region insulating layer on the channel structures, studs penetrating through the cell region insulating layer and connected to the channel structures, respectively, first separation regions penetrating through the gate electrodes, and a second separation region penetrating through the upper gate electrode between the studs, wherein side surfaces of the second separation region include round portions and straight portions between the round portions, each of the gate electrodes includes a first conductive layer and a second conductive layer, and the second separation region is in contact with the first conductive layer and the second conductive layer of the upper gate electrode.