3D Memory Multi-Deck Structure for Easier Gate Slit Etching
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Solution Overview
Problem
Existing 3D NAND memory devices with multi-deck structures face challenges in forming gate line slits with high aspect ratios due to the increased number of conductor/dielectric layer pairs, leading to difficulties in material removal and performance issues.
Innovation Solution
The 3D memory device employs a multi-deck structure with alternating conductor and dielectric layers, forming slit openings and source structures by depositing dielectric decks and removing sacrificial layers, which reduces the impact of layer count on fabrication and allows for the formation of staggered portions, thereby simplifying the etching process and reducing fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of conductor/dielectric layer pairs is increased to enhance storage capacity, then storage density is improved, but the aspect ratio of gate line slits increases making material removal difficult
Solution Approach 1:
The gate line slit formation process is segmented into multiple etching stages corresponding to different deck levels. Instead of forming one continuous high aspect ratio slit through all layers, the process creates intermediate slits at each deck interface, breaking the single difficult operation into multiple manageable steps that reduce material removal challenges at each stage.
Solution Approach 2:
Sacrificial layers are deposited and patterned in advance before the final gate line slit etching. These preliminary sacrificial structures serve as etch stops and guides, enabling controlled material removal through the multi-deck structure without requiring direct etching through the entire high aspect ratio path in a single step.
2Quantity of substance
If more conductor/dielectric layer pairs are stacked vertically, then memory density increases, but fabrication complexity and process difficulty increase
Solution Approach 1:
The fabrication process is divided into modular deck formation steps, where each deck (set of conductor/dielectric layers) is processed independently through standardized sequences of deposition, patterning, and etching. This modular approach allows the same fabrication procedures to be repeated for multiple decks, managing complexity through process standardization and modularity.
Solution Approach 2:
Multiple decks are nested vertically within a single memory structure, with each deck containing complete memory cell functionality. The nested arrangement allows high memory density to be achieved by stacking functional units, while the repetitive nature of the nested structure enables efficient fabrication through process reuse across all deck levels.
3Length of stationary object
If high aspect ratio slits are formed through many layers, then vertical integration is achieved, but etching process difficulty and time increase
Solution Approach 1:
The continuous vertical etching path is segmented into discrete etching operations at each deck level. By creating intermediate slits and using sacrificial layers at deck interfaces, the single long etching operation is divided into multiple shorter etching steps, reducing the cumulative etching time and process difficulty while achieving the same vertical integration.
Solution Approach 2:
Sacrificial layers serve as intermediary structures that facilitate the etching process. These temporary materials are deposited between deck levels and removed selectively to create etch stops and guides, enabling controlled material removal through the multi-deck structure without requiring direct etching through the entire vertical distance in a single operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of 3D memory devices with improved fabrication efficiency and reduced complexity, maintaining performance by minimizing the challenges associated with high aspect ratios and layer count, thus enhancing storage capacity and reducing costs.
Implementation Method 1
depositing dielectric decks
Implementation Method 2
depositing dielectric decks
Data Source
AI summary
Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a substrate and a stack structure in an insulating structure on the substrate. The stack structure includes alternating a plurality of conductor layers and a plurality of insulating layers. The 3D memory device further includes a source structure extending vertically through the alternating stack structure. The source structure includes at least one staggered portion along a respective sidewall. The 3D memory device further includes a channel structure and a support pillar each extending vertically through the alternating stack structure and a plurality of contact structures extending vertically through the insulating structure.