3D Memory Gate Stack Layout for Higher-Density Bit Line Contacting
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Solution Overview
Problem
The demand for high-capacity data storage in integrated circuit devices is limited by the integration of two-dimensional memory devices, which is constrained by the cost of fine patterning equipment and the limited area of chip dies, prompting the need for a three-dimensional vertical memory device structure.
Innovation Solution
An integrated circuit device with a base structure, gate stack, channel structures that penetrate the gate stack, and a specific insulating layer configuration, including a first and second upper insulating layer with a buried insulating pattern, supports a bit line and bit line contacts to enhance data storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory device integration is increased, then data storage capacity is improved, but manufacturing cost increases due to expensive fine patterning equipment
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertical structure by stacking gate electrodes and channel structures vertically. The gate electrodes are arranged in multiple layers along the vertical direction, with channel structures penetrating through them, creating a vertical NAND flash memory architecture that increases storage capacity without requiring finer lateral patterning
2Quantity of substance
If two-dimensional memory device integration is increased, then data storage capacity is improved, but chip die area is fully utilized leaving no room for further integration
Solution Approach 1:
The invention utilizes the vertical dimension by stacking multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode, etc.) and channel structures vertically above each other. This three-dimensional arrangement allows continuous increase of storage capacity without expanding lateral chip area, as memory cells are arranged in vertical columns rather than horizontal planes
3Manufacturing precision
If vertical memory device structure is implemented, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The vertical memory structure is divided into segmented components: multiple discrete gate electrodes (first, second, third gate electrodes) spaced apart vertically, channel structures penetrating through them, and insulating layers separating each layer. This segmentation allows independent formation and control of each vertical layer, simplifying the manufacturing process compared to attempting to create a monolithic vertical structure
Solution Approach 2:
The patent forms insulating layers between the gate electrodes before completing the full vertical stack. This preliminary formation of insulating structures provides a foundation and spacing reference for subsequent gate electrode and channel structure formation, making the overall manufacturing process more manageable and precise
Data Source
AI summary
An integrated circuit device comprising a base structure, a gate stack on the base structure and comprising a plurality of gate electrodes spaced apart from each other, a first upper insulating layer on the gate stack, a plurality of channel structures that penetrate the gate stack, each of the plurality of channel structures comprises a respective alignment key protruding from the gate stack, a second upper insulating layer that overlaps the respective alignment key of each of the plurality of channel structures, a top supporting layer on the second upper insulating layer, a bit line on the top supporting layer, and a plurality of bit line contacts that electrically connect respective ones of the plurality of channel structures to the bit line. A sidewall of the first upper insulating layer includes a first step.